Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2000-01-03
2002-03-26
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C708S491000
Reexamination Certificate
active
06363471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address generation mechanisms within processors.
2. Description of the Related Art
Processors are generally designed in accordance with an instruction set architecture, which specifies the instructions, the format of the instructions, and other resources used by the processor in executing instructions. Additionally, the instruction set architecture may specify the execution environment, including such features as the address translation mechanism, etc.
A popular instruction set architecture is the x86 instruction set architecture. Due to the wide acceptance of the x86 instruction set architecture in the computer industry, many processor designers select the x86 instruction set architecture when designing processors. The x86 instruction set architecture has been revised over time to expand the capabilities of the instruction set. For example, the x86 instruction set architecture was initially a sixteen bit instruction set architecture: the maximum size operands handled were 16 bit, and memory was addressed using a 16 bit address as well. Over time, the x86 instruction set architecture has been expanded to 32 bits. However, compatibility with the 16 bit mode was maintained to support software written for the earlier instruction set architecture. While compatibility is desirable, it creates complications in the design of processors implementing the instruction set architecture.
One such complication involves the generation of addresses of memory operands. Generally, an instruction may have one or more source operands upon which the instruction operates to produce a result (a destination operand). Operand are register operands if they are stored in a register defined by the instruction set architecture, or memory operands if they are stored in a memory location of a memory to which the processor may be coupled. If an instruction has a memory operand, it typically includes one or more address operands which are used to form the memory address at which the memory operand is stored. The address operands may include, for example, one or more of the following: a displacement (which is a value coded directly into the instruction), a base register operand, and an index register operand. The sum of the address operands forms a logical address. The logical address is translated through a segmentation mechanism to a linear address (also referred to herein as a virtual address). The segmentation mechanism comprises selecting a segment register according to the instruction, and adding a corresponding segment base address (or simply segment base) to the logical address to produce the virtual address. The virtual address may subsequently be translated through a paging mechanism to a physical address. The physical address is the address presented to the memory to identify the corresponding storage location.
It is desireable to generate the virtual addresses as quickly as possible in order to accelerate access to memory operands. However, the generation of virtual addresses is hindered by the existence of multiple addressing modes in the x86 instruction set architecture. The addressing modes are used to provide compatibility with the earlier 16 bit addressing while allowing 32 bit addressing as well. Generally, an addressing mode specifies the number of bits present in the address operands. More particularly, the code segment (which translates logical instruction fetch addresses to linear instruction fetch addresses in a manner similar to the generation of memory operand addresses) specifies a default addressing mode for each instruction. However, using an address override prefix byte, a particular instruction may reverse the default addressing mode. Thus, the addressing mode is determined on an instruction-by-instruction basis.
In the 16 bit addressing mode, the logical address is formed by adding the address operands of the instruction (as 16 bit quantities). Any carries from the sixteenth bit are discarded. The resulting 16 bit logical address is added to the segment base, which is a 32 bit quantity in the present x86 instruction set architecture, respecting any carry into the seventeenth bit of the virtual address sum. On the other hand, in 32 bit addressing mode, the address operands are 32 bit. Accordingly, the virtual address is a 32 bit sum of the segment base and the address operands. The differences in handling 16 bit and 32 bit addressing mode, particularly the discarding of carries when adding the address operands but the preservation of the carry when adding the segment base in 16 bit addressing mode, adds complication to the generation of memory operand addresses. This complication tends to slow the generation of addresses, thereby reducing the speed at which memory operands may be accessed.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a processor as described herein. The processor includes an address generation unit (AGU) which adds address operands and the segment base. The AGU may add the segment base and the displacement while other address operands are being read from the register file. The sum of the segment base and the displacement may subsequently be added to the remaining address operands. The AGU receives the addressing mode of the instruction, and if the addressing mode is 16 bit, the AGU zeros the carry from the sixteenth bit to the seventeenth bit of the sums generated therein. Additionally, in parallel, the AGU determines if a carry from the sixteenth bit to the seventeenth bit would occur if the logical address were added to the segment base. In one embodiment, the sum of the address operands and the segment base, with carries from the sixteenth bit to the seventeenth bit zeroed, and the carry generated in parallel are provided to a translation lookaside buffer (TLB), which stores translations in the same format (sum and carry). In another embodiment, the AGU corrects the most significant bits of the generated sum based on the carry. The AGU and/or TLB may provide reduced address generation latency while handling the 16 bit addressing mode as defined in the instruction set architecture.
Broadly speaking, a processor is contemplated, the processor comprising an AGU. The AGU is coupled to receive a segment base, one or more address operands of an instruction, and a mode signal identifying whether or not an addressing mode of the instruction is 16 bit. The AGU includes adder circuitry configured to add the segment base and the one or more address operands to produce a value, and further configured to zero a carry-in to a seventeenth bit of the value in response to the mode signal indicating that the addressing mode is 16 bit. The AGU further includes a carry circuit configured to generate a first carry signal indicative of a carry-in to the seventeenth bit of a virtual address of a memory operand of the instruction according to an instruction set architecture defining the instruction. The carry circuit is coupled to receive the mode signal and to generate the first carry signal in response to the mode signal. Additionally, a computer system is contemplated including the processor and an input/output (I/O) device configured to communicate between the computer system and another computer system to which the I/O device is couplable.
Moreover, a method is contemplated. One or more address operands of an instruction and a segment base are summed to produce a value, wherein the summing comprises zeroing a carry-in to a seventeenth bit of the value responsive to an addressing mode of the instruction being 16 bit. A first carry-in to the seventeenth bit of a virtual address of a memory operand of the instruction is generated according to an instruction set architecture defining the instruction and in response to the addressing mode.
REFERENCES:
patent: 5233553 (1993-08-01), Shak et al.
patent: 5408626 (1995-04-01), Dixit
patent: 5511017 (1996-04-01), Cohen et al.
patent: 5612911 (1997-03-01), Timko
patent: 5
Gieseke Bruce A.
Haddad Ramsey W.
McGee William A.
Meier Stephan G.
Advanced Micro Devices , Inc.
Merkel Lawrence J.
Moazzami Nasser
Yoo Do Hyun
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