Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-03-30
2003-11-18
Portka, Gary J (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C211S151000, C211S208000
Reexamination Certificate
active
06651156
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of memory management within a computing system, and more particularly to an apparatus and method for extending the properties of virtual memory pages above and beyond those provided for by an existing translation lookaside buffer architecture.
2. Description of the Related Art
Early computing systems executed application programs that were composed especially to run on those systems. The programs consisted of a sequence of instructions that were loaded into the memory of the computing system at the time of execution. Address logic within the computing system would generate a memory address each time an instruction was fetched from the memory for execution. Access logic within the computing system would place the memory address out on a memory address bus and the memory would provide the contents of the memory location corresponding to the memory address for execution by the computing system. In addition to program instructions, the early computing systems employed memory locations to temporarily store data that was used by application programs. And like the retrieval of program instructions for execution, the storage and retrieval of program data involved the generation of memory addresses that corresponded to data memory locations.
The memory addresses generated by the address logic were directly routed to the early computing systems' memory busses to access corresponding memory locations. Hence, to access location 10513BC7h in memory required that the address logic generate address 10513BC7h and issue this address to the memory bus. But stated differently, it also is true that when the address logic generated address 10513BC7h, the memory location to which this address corresponded was also location 10513BC7h.
It is intuitive to observe that a direct, one-to-one correspondence between memory addresses generated by a program executing on an early computing system and locations in the computing system's memory was quickly deemed disadvantageous from many standpoints. First, in order to execute a wide variety of application programs, it was required that the early computing system always provide memory that spanned the full address range of the system. Second, such correspondence unnecessarily coupled the architecture of the computing system to the tools that were used to produce and execute programs on the system. For instance, programs required modifications in order to execute on computing systems that exhibited different memory ranges and constraints. And finally, as computers progressed to the point of providing time-share (i.e., multi-tasking) operating systems, performance degradations were observed since all memory management and protection functions had to be performed by the operating systems.
Virtual memory techniques were developed during the mid-1970's specifically to address the above-noted problems. Stated briefly, a virtual memory “manager” within a computing processing unit (CPU) served as an intermediary between address generation logic in the CPU and access logic that accessed memory locations. Under a virtual memory management scheme, a “virtual address” generated by the address logic was “translated” according to a predefined and configurable mapping strategy into a “physical address” that was placed on the memory bus to access a corresponding memory location. Hence, virtual memory management solved the problem of one-to-one correspondence.
Virtual memory management techniques continue to provide benefits today that enable the operating system of a computing system to effectively control where application programs are loaded and executed from memory in addition to providing a means whereby memory can be assigned to a program while it is running and then released back into the memory pool when the memory is no longer necessary. Most virtual memory management units today divide a system's virtual memory into equal-sized chunks called memory pages. To access a memory page requires translation of the upper bits of a virtual address; the lower bits of the virtual address are not translated and merely represent an offset into a page.
Virtual memory management not only applies to the locations associated with memory, but also to the properties, or attributes, associated with those locations. For instance, a virtual page may be designated for reads only so that data writes to locations in the page can be precluded.
The virtual-to-physical address mapping information, along with information specifying the attributes of virtual memory pages, are stored in a designated area of memory known as a page table. Generally speaking, a page table contains one entry for each virtual memory page within the address space of a CPU. Hence, for each memory access, it is required that the page table entry associated with the access be retrieved so that the virtual address can be translated into a physical address and so that access attributes can be determined.
Translation lookaside buffers (TLBs) were incorporated into CPU designs for the express purpose of storing frequently used page table entries within a CPU so that memory accesses are not required each time an address is generated. A TLB is a very fast memory providing storage for a number of page table entries. TLBs are designed to be efficient and fast because they typically lie in the critical timing path of a CPU. Accordingly, only those information bits that are essential to the translation of addresses and specification of memory page attributes are provided in a page table entry within a TLB.
TLBs are streamlined to support rapid access for the translation of addresses. As a result, however, the structure of a given TLB is quite static, yielding little or no room for expansion. Hence, if it is desired to update the design of a CPU to incorporate a newly developed or expanded set of memory properties, then it is highly probable that the design of the CPU's TLB must be modified to provide for expression of the properties at the virtual page level. But for CPU's that have relegated TLB management tasks to operating system software, changing the structure of an existing TLB creates incompatibilities with the operating system software—the operating system must be updated in order to provide for memory management according to the new/expanded memory properties.
A significant market segment is lost, however, when an upgraded CPU becomes no longer compatible with an older operating system and its application programs. CPU manufacturers desire, at least, that CPU upgrades retain compatibility with older software. But compatibility retention in the case of a software-managed TLB architecture implies that the number of virtual memory attributes that are provided in a upgraded design be limited by the existing TLB structure. In other words, to retain compatibility with an older operating system means that little or no virtual page management features can be implemented in an upgraded CPU design.
Therefore, what is needed is an apparatus that allows expanded memory attributes to be provided via an existing TLB design, where the number of attributes exceeds the structure of the TLB, and where the structure of the TLB is maintained for compatibility with legacy software.
In addition, what is needed is a mechanism for extending the properties of virtual memory pages that utilizes an existing TLB structure.
Furthermore, what is needed is a CPU apparatus that allows more virtual memory page properties to be exercised than what an existing TLB structure accommodates, where the TLB structure also is backwards compatible with older operating system software.
Moreover, what is needed is a method for extending virtual memory page properties beyond the capacity of an existing TLB, but which defaults to states that can be interpreted by legacy applications software.
SUMMARY OF THE INVENTION
The present invention provides a superior technique for extending the properties of virtual memory pages beyond that provided
Courtright David A.
Hudepohl Lawrence H.
Kissell Kevin D.
Uhler G. Michael
Huffman James W.
Huffman Richard K.
MIPS Technologies Inc.
Portka Gary J
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