Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2006-03-14
2006-03-14
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S208000
Reexamination Certificate
active
07013382
ABSTRACT:
For use in a wide-issue pipelined processor, a mechanism and method for reducing pipeline stalls between nested calls and supporting early prefetching of instructions in nested subroutines and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a program counter (PC) generator that generates return PC values for call instructions in a pipeline of the processor and (2) return PC storage, coupled to the PC generator and located in an execution core of said processor, that stores the return PC values and makes ones of the return PC values available to a PC of the processor upon execution of corresponding return instructions.
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Hitt Gaines PC
LSI Logic Corporation
Tsai Henry W. H.
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