Computer graphics processing and selective visual display system – Computer graphics display memory system – Logical operations
Reexamination Certificate
2000-09-28
2003-10-07
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Logical operations
C345S505000, C345S520000, C345S531000
Reexamination Certificate
active
06630936
ABSTRACT:
TECHNICAL FIELD
The present invention relates to computer system architecture, and more particularly, relates to a mechanism and a method for enabling two graphics controllers to each execute in parallel a portion of a single block transform (BLT) in a computer system.
BACKGROUND
One of the most common operations in computer graphics applications is the Block Transform (often referred to as a “BLT” or “pixel BLT”) used to transfer a block of pixel data from one portion (the “source”
12
) of a graphics surface
10
of a display memory to another (the “destination”
14
) as shown in
FIG. 1. A
series of source addresses are generated along with a corresponding series of destination addresses. Source data (pixels) are read from the source addresses, and then written to the destination addresses. In addition to simply transferring data, a BLT operation may also perform a logical operation on the source data (pixels) and other OPEPAND(s) (often referred to as a raster operation, or ROP). ROPs and BLTs are discussed in Computer Graphics Principles and Practice, Second Edition, by Foley, VanDam, Feiner and Hughes, Addison-Wesley Publishing Company, Inc., 1993, pp. 56-60. BLT operations are commonly used in creating or manipulating images in computer systems, such as color conversion, stretching and clipping of images. The implementation of a ROP in conjunction with a BLT operation is typically performed by coupling source and/or destination data to one or more logic circuits which perform a logical operation according to a ROP command requested. There are numerous possible types of ROPs used to combine the source data, pattern and destination data. See Richard F. Ferraro, Programmer's Guide to the EGA, VGA and Super VGA Cards, Third Edition, Addison-Wesley Publishing Company, Inc., 1994, pp. 707-712. In addition to standard logic ROPs, arithmetic addition or subtraction has also been implemented in computer systems. Similarly, a common “Windows” pattern known as a brush may also be included in addition to destination data. The brush pattern is typically a square of pixels arranged in rows which is used for background fill in windows on a display screen. The brush pattern may be copied to the destination data, or may be combined with the destination data in other ways, depending on the type of ROPs specified.
BLT and related operations are typically performed along with other graphics operations by specialized hardware of a computer system, such as a graphics controller. The particular hardware that undertakes BLT and related operations is commonly referred to as a graphics engine which resides in the graphics controller. Basic BLT operations (with a ROP) may include general steps of: reading source data from the source
12
to a temporary data storage, optionally reading destination data or other OPERAND data from its location, performing the ROP on the data, and writing the result to the destination
14
.
The source
12
and destination
14
may be allowed to overlap in an overlap region
16
as shown in FIG.
2
. The value of the source pixels and destination pixels prior to the BLT operation must, however, be used to calculate the new value of the destination pixels. In other words, the state of the graphics surface
10
after the BLT operation must be as if the result were first calculated and stored into a temporary data storage for the entire destination
14
and then copied to the destination
14
.
Conventional computer systems deal with overlapping source
12
and destination
14
by copying the “leading edge” of the source
12
to the destination
14
. As a result, all pixels are read as a source
12
before being written as a destination
14
. However, if an additional graphics controller is incorporated into, or plugged-in an expansion board of an existing computer system for advanced graphics applications, synchronization and coherency problems exist with two graphics controllers working on the same surface simply to get the correct result, even if performance were not an issue. If the operation is serialized to ensure that pixels that are both source and destination are read as a source before being written as a destination, then the performance advantage of multiple graphics controllers in a single computer system will be reduced.
Accordingly, a need exists for multiple graphics controllers in a hybrid model computer system to establish proper synchronization, and to efficiently allocate and share the same image rendering tasks for coherency, particularly when dealing with overlapping source and destination regions during BLT and related operations.
REFERENCES:
patent: 5640578 (1997-06-01), Balmer et al.
patent: 5919256 (1999-07-01), Widigen et al.
patent: 5940087 (1999-08-01), Katsura et al.
patent: 5943064 (1999-08-01), Hong
patent: 5995121 (1999-11-01), Alcorn et al.
patent: 6008823 (1999-12-01), Rhoden et al.
patent: 6389504 (2002-05-01), Tucker et al.
Antonelli Terry Stout & Kraus LLP
Bui, Esq. Hung H.
Tung Kee M.
LandOfFree
Mechanism and method for enabling two graphics controllers... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism and method for enabling two graphics controllers..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism and method for enabling two graphics controllers... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3151199