Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
2001-06-05
2003-01-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S737000, C438S666000
Reexamination Certificate
active
06512293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to packaging semiconductor devices, and more particularly to ball grid array type semiconductor packages.
BACKGROUND OF THE INVENTION
Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Ball grid array (BGA) packages are constructed with die mounted on a substrate with bond pads on the die connected to conductive lines or traces on the surface substrate. These substrates may be either ceramic, printed circuit board laminate, or tape.
An array of solder balls mounted on the bottom of the substrate are used to attach the package to a PC board or motherboard, as opposed to molded plastic packages that use lead frames on the outer edges of the package substrate to attach the package to the PC board. Mounting the balls on the bottom of the package substrate reduces package size and decreases lead pitch, leading to higher assembly yields.
Although BGA packages are improvement over molded plastic packages, BGA packages have certain disadvantages. One disadvantage is that BGA packages must be placed on a PC board individually, which increases manufacturing time and cost. Another disadvantage is that BGA packages require a clearance between individual packages on the PC board, which increases the required size of the PC board.
Accordingly, what is needed is an improved ball grid array package. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a ball grid array assembly formed from interlocking ball grid array packages, wherein each of the ball grid array packages has interlocking edge features for mechanical connection. The plurality of ball grid array packages are joined via the interlocking edge features to form an interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.
According to the system and method disclosed herein, the present invention provides a more efficient and cost effective method of using multiple ball grid array packages in an assembly.
REFERENCES:
patent: 5834843 (1998-11-01), Mori et al.
patent: 2001/0051449 (2001-12-01), Davison et al.
U.S. patent application Ser. No. 09/888,266, Davision et al., filed Dec. 2001.
Chia Chok J.
Liew Wee K.
Lim Seng Sooi
LSI Logic Corporation
Owens Douglas W.
Sawyer Law Group LLP
Thomas Tom
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