Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2005-06-28
2009-11-24
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S106000, C257SE21521
Reexamination Certificate
active
07622309
ABSTRACT:
A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.
REFERENCES:
patent: 5503286 (1996-04-01), Nye et al.
patent: 6028357 (2000-02-01), Moriyama
patent: 6077765 (2000-06-01), Naya
patent: 6137174 (2000-10-01), Chiang et al.
patent: 6413878 (2002-07-01), Woolsey et al.
patent: 6436300 (2002-08-01), Woolsey et al.
patent: 2002/0050378 (2002-05-01), Chiang et al.
patent: 2004/0020045 (2004-02-01), Hirano
patent: 2004/0072387 (2004-04-01), Hong et al.
patent: 2005/0082577 (2005-04-01), Usui
patent: 2005/0112794 (2005-05-01), Cole et al.
K. Hess, et al., U.S. Appl. No. 11/033,009, filed Jan. 11, 2005, entitled “Integrated Circuit Having Structural Support for a Flip-Chip Interconnect Pad and Method Therefor,”.
K. Chang, et al., “Improvements of Solder Ball Shear Strength of a Wafer-Level CSP Using a Novel Cu Stud Technology,” IEEE Transactions on Components and Packaging Technologies, vol. 27, No. 2, Jun. 2004.
Pozder Scott K.
Su Peng
Wontor David G.
Zhao Jie-Hua
Cannatti Michael Rocco
Freescale Semiconductor Inc.
Hamilton & Terrile LLP
Trinh Michael
LandOfFree
Mechanical integrity evaluation of low-k devices with bump... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanical integrity evaluation of low-k devices with bump..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanical integrity evaluation of low-k devices with bump... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4139300