Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
1999-09-03
2002-11-05
Lee, Thomas (Department: 2787)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S501000
Reexamination Certificate
active
06477659
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to testing of digital systems. More specifically, the present invention relates to a method and an apparatus for measuring timing margins within a digital system by varying a programmable clock skew between components in the digital system.
2. Related Art
As computer system clock speeds continue to increase at an exponential rate, the timing margins for signals passing between computer system components are becoming progressively smaller. This makes computer systems increasingly sensitive to variations in the propagation delay in the signals passing between computer system components. These variations can be caused by a number of factors, including changes in operating parameters, such as temperature and voltage. These variations can also be caused by slight variations in the computer system components that are collectively assembled into a computer system. For example, if the computer system components are located on the same semiconductor chip, variations during the semiconductor manufacturing process can cause variations in propagation delay through the individual computer system components.
If the propagation delay for a signal falls outside of a safe range, the signal may arrive too early or too late at a given computer system component. This can cause the wrong value to be stored in a memory element, which can cause the computer system to produce an erroneous result.
Computer systems can be tested in a number of ways to determine whether or not they will operate properly. A computer system can be tested at different clock speeds. For example, the clock speed can be increased until the computer system stops operating correctly. The computer system is then certified to operate at a clock speed that is lower than this maximum possible value. The problem with this type of testing is that many critical timing paths are not clock dependent. Hence, timing margins on these critical timing paths cannot be measured by varying the clock speed.
Alternatively, a computer system can be tested in different operating environments by varying parameters such as voltage and temperature. Unfortunately, this type of testing cannot measure timing margins, because timing parameters of interdependent components will often change together in a complementary way as voltage and/or temperate change.
To ensure that computer system components will continue to operate properly in different system configurations and operating environments, it is necessary to accurately measure timing margins. Simply knowing that the device operates properly in a given environment or configuration is not sufficient. Even if a device operates properly, a timing margin for a critical signal can be extremely narrow. If this is the case, a small variation in the propagation delay of the critical signal causes the timing margin to be exceeded, and can thereby cause the system to fail.
Automatic testing equipment (ATE) systems are often used to measure timing margins on critical paths through devices within a computer system. However, ATE systems are limited to measuring timing between signals as they appear on the I/O pins of a semiconductor chip, or on the interface pins on a circuit module. Hence, ATE systems are not capable of measuring timing margins between internal functional blocks within a chip or within a circuit module.
Another alternative is to use simulation software to simulate timing margins between components within a semiconductor chip before the chip is fabricated. However, simulation programs run extremely slowly, typically many thousands and possibly millions of times slower than the circuitry that is being simulated. Hence, only a limited number of test cases can be simulated. Furthermore, the models used for simulations are not entirely accurate, and simulations do not accurately account for process variations during manufacture of the semiconductor chip, which can affect propagation delays.
What is needed is a method and an apparatus for measuring timing margins along critical signal paths between components within a digital system.
SUMMARY
One embodiment of the present invention provides a system that measures timing margins within a digital system by varying a clock skew between components in the digital system. The system receives a reference clock signal as an input. This reference clock signal is used to generate a first clock signal and a second clock signal so that there exists a programmable skew between the first clock signal and the second clock signal. The first clock signal is used to drive a first component, and the second clock signal is used to drive a second component in the digital system. The system measures an upper margin for the clock skew by iteratively increasing the clock skew and testing the system to verify that it operates correctly. When the digital system stops operating correctly, the upper margin is set to be the amount by which the clock skew was increased before the digital system stopped operating correctly.
In one embodiment of the present invention, the system measures a lower margin for the clock skew by iteratively decreasing the clock skew and testing the system to verify that it operates correctly. When the digital system ultimately stops operating correctly, the lower margin is set to be the amount by which the clock skew was decreased before the digital system stopped operating correctly.
In a variation on the above embodiment, the system uses the upper margin and the lower margin to compute a substantially optimum clock skew value, and then sets the clock skew to the substantially optimum clock skew value for subsequent operation of the digital system.
In another variation on the above embodiment, the system computes a function of the upper margin and the lower margin of the clock skew to determine if the digital system has acceptable timing margins.
In one embodiment of the present invention, the system generates the first clock signal by adding a first delay to the reference clock signal. The system correspondingly generates the second clock signal by adding a second delay to the reference clock signal.
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Cao Chun
Lee Thomas
Park, Vaughn & Fleming LLP
Sun Microsystems Inc.
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