Measuring input setup and hold time using an input-output...

Details Measuring input setup and hold time using an input-output... Measuring input setup and hold time using an input-output...

2006-11-21

2006-11-21

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S093000, C327S141000

Reexamination Certificate

active

07138829

ABSTRACT:
A system and method for measuring the timing requirements of a sequential logic element of a programmable logic device. The sequential logic element has a first data terminal, an output terminal, and a clock terminal. A first synchronous element is coupled to the data terminal through a first delay element. The first synchronous element is clocked by a clock signal and receives an alternating test signal. A second synchronous element is coupled to the clock terminal through a second delay element of an input-output block. The second synchronous element is also clocked by the clock signal and receives the alternating test signal. The output terminal of the sequential logic element is monitored by a tester or by logic configured in the fabric of the programmable logic device to determine when the logic state changes as the delay of the first or second delay element is selectively varied.

REFERENCES:
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patent: 6239611 (2001-05-01), Matera
patent: 6564360 (2003-05-01), Chiu
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U.S. Appl. No. 10/990,045, filed Nov. 16, 2004, Dalvi.
Xilinx, Inc.; Virtex 4 User Guide; (v1.1); Sep. 10, 2004; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-43.

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