Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Patent
1999-03-18
2000-09-05
Chaudhari, Chandra
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
438250, 438591, H01L 2166
Patent
active
061141828
ABSTRACT:
A resist pattern having a high-density pattern area and a low-density pattern area is formed on a layered MNOS capacitor structure composed of a Ti(O)N layer and a WSi.sub.2 layer formed on nitride/oxide insulating layer on a semiconductor substrate. After the etching of the layered structure in the low-density resist pattern area is finished, the layered structure is further processed with plasma of HBr only, a mixed gas of a halogen-containing gas and oxygen gas, or a fluorine-containing gas, for a desired period of time, to give electron shading damage. In this plasma processing, the Ti(O)N layer is etched little. The electron shading damage is measured through the change in the flat band voltage of the MNOS capacitor.
REFERENCES:
patent: 3893152 (1975-07-01), Lin
patent: 4151537 (1979-04-01), Goldman et al.
patent: 4840917 (1989-06-01), Sheu
Concise Explanation of Relevent Portions of References--2 pages.
Suguru Tabara, A New Etching Method for Reducing the Electron Shading Damage Using ICP Etcher, May 13-14, 1996, pp. 51-53.
Koichi Hashimoto, New Phenemona of Charge Damage in Plasma Etching: Heavy Damage Only through Dense-Line Antenna, Dec. 1993, pp. 6109-6113.
Koichi Hashimoto, Charge Damage Caused by Electron Shading Effect, Oct. 1994, pp. 6013-6018.
Chaudhari Chandra
Yamaha Corporation
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