Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-03
2003-11-25
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S128000, C438S598000, C438S618000, C438S637000
Reexamination Certificate
active
06653214
ABSTRACT:
RIGHTS OF THE GOVERNMENT
The invention described herein may be manufactured and used by or for the Government of the United States for all governmental purposes without the payment of any royalty.
BACKGROUND OF THE INVENTION
In fabricating Monolithic Microwave Integrated Circuit (MMIC) devices and other integrated circuit devices of the type capable of processing large signals in the radio frequency range above 1 gigahertz for example, the presence of uncontrolled small electrical resistances and inductances (i.e., generically speaking “impedances”) in random and unexpected portions of a circuit can have a profound effect on circuit operation. As the frequency of operation increases up to and above 100 gigahertz the parasitic resistances and inductances have increasing impact on circuit performance. Such uncontrolled impedances may, however, easily arise with the use of via-hole structures for connecting upper and lower surfaces of the integrated circuit wafer on which a circuit is fabricated. The presence of such uncontrolled impedances in a particularly critical location of an amplifier circuit may, for example, determine whether the amplifier behaves as the intended signal amplifier or as a signal source, i.e., as an oscillator. The reverse condition is also true with a circuit intended to perform as an oscillator performing instead as an amplifier as a result of via-hole dimensional changes. A particularly difficult aspect of this behavior arises from the fact that such circuit performance changes may occur randomly over a group of fabricated integrated circuit devices without apparent cause until a significant amount of investigation discloses the presence of critical impedance variations relating to physical size tolerances in via-hole conductor elements. Variations in amplifier gain, amplifier phase shift characteristics, transmission line standing wave ratio and other performance changes may arise from via-hole conductor element tolerances that are manifest as slightly differing physical sizes and slightly altered electrical parameter magnitudes.
The frequent radio frequency circuit practice of operating the emitter terminal of a bipolar junction transistor or the source terminal of a field effect transistor in a grounded electrical potential condition contributes perhaps significantly to the via-hole tolerance difficulty since such transistor grounding is often accomplished by way of a via-hole-embodied conductor traversing the thickness of a wafer or a substrate to make connection with the ground plane element disposed over the backside of the radio frequency integrated circuit device. Such ground plane elements although desirable from a transmission line characteristics viewpoint also support the need for via-hole conductors and thus foster the introduction of an added integrated circuit fabrication variable into circuit performance.
The practice of wafer thinning as is often used in Microwave Monolithic Integrated Circuits (MMIC) and other integrated circuit arrangements is useful for obtaining more desirable transmission line characteristics, for heat conduction enhancement and for limiting the length of via-hole conductors for example. Thinning of a substrate from a thickness of about 625 micrometers (&mgr;m) to a thickness of about 100 &mgr;m or to as thin as 25 &mgr;m may be practiced in the radio frequency integrated circuit art. Additional details concerning the practice of wafer thinning are disclosed in the above-identified companion and incorporated by reference herein patent application. The use of wafer thinning although helpful in limiting via-hole conductor length dimensions is also a source of increased via-hole diameter tolerance difficulties because wafers which have been thinned also tend to have greater thickness variations. Such thickness variations can relate directly to via-hole diameter changes and thereby give rise to the circuit performance variations desirably minimized herein. These via-hole diameter variations arise when via-holes are fabricated through use of the usual timed etching process i.e., when an unusually thin wafer location is etched-through more quickly than other portions of the wafer during the allowed etching time and the etching reagent is thus provided with a greater duration of hole-enlargement time at the completion of its vertical etch travel in the thin wafer location than in the normal or thicker wafer locations.
Since a significant part of the advantages offered by realization of electronic apparatus with integrated circuit devices arises from the short lead lengths and the relatively precise repeatability of component characteristics in the integrated circuit fabrication process, the introduction of a significant “new” variable impedances element as described in these paragraphs is particularly unwelcome-especially in devices operating in the high radio frequency range from microwave upward. The present invention provides control of the via-hole conductor size and impedance variables, an arrangement implementable without new or additional wafer processing steps and thus with desirable low overhead cost. The present invention provides an etching assistance tool that may be used to overcome or limit the effect of these via-hole dimension and electrical characteristics variations.
The present invention provides an arrangement for controlling this via conductor impedance variable through controlling the achieved dimensions of a substrate via-hole. The invention provides an etching vernier pattern that can be placed in the via-hole to allow ex-situ monitoring of the via-hole formation etching process and thus determine the size of the subsequent via conductor. Furthermore, the achieved etching vernier also provide a measure of via-hole diameter variation across a substrate.
SUMMARY OF THE INVENTION
The present invention provides an arrangement for controlling the variation in electrical impedance presented by a small diameter via-hole and a larger via-hole through controlling the achieved dimensions of a via-hole. The invention provides an etching vernier disposable in the via-hole to allow precise monitoring of the via-hole etching process. Furthermore, the achieved etching vernier will also provide a measure of the via-hole diameter variation across a given substrate. Such via-hole dimensional change data may also be a useful tool for process development and control through a statistical process control (SPC) methodology.
It is therefore an object of the invention to provide an integrated circuit wafer etching vernier pattern.
It is another object of the invention to provide a via-hole measurement arrangement that is usable during via-hole etching.
It is another object of the invention to provide an etched cavity measurement pattern of particularly useful physical configuration.
It is another object of the invention to provide an etching vernier capable of identifying a properly etched via-hole condition in a substrate.
It is another object of the invention to provide an etching vernier capable of identifying both an over etched and an under etched via-hole condition in a substrate.
It is another object of the invention to provide an etch measurement pattern having precise physical measurement standards included therein.
It is another object of the invention to provide an integrated circuit wafer etching vernier pattern usable to indicate wafer thickness variations.
It is another object of the invention to provide an etching vernier that is useful in identifying a wafer etching mask misalignment condition.
It is another object of the invention to provide an etching vernier capable of providing etch progression information near the end of an etching event when such information is particularly useful.
It is another object of the invention to provide a metallic pattern etching vernier for an integrated circuit wafer.
It is another object of the invention to provide an integrated circuit etching vernier metallic pattern that is compatible with normal wafer processing and requiring of no additional integrated circuit devi
Bozada Christopher A.
DeSalvo Gregory C.
Dettmer Ross W.
Ebel John L.
Gillespie James K.
Guerrero Maria
Hollins Gerald B.
Kundert Thomas L.
The United States of America as represented by the Secretary of
Zarabian Amir
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