Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-10-14
2002-09-10
Kim, Matthew (Department: 2186)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S308000, C711S154000, C711S213000, C711S217000
Reexamination Certificate
active
06449665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to direct memory access in a digital system, such as a printer. More particularly, this invention relates to a method of reducing direct memory access.
2. The Prior Art
Many existing computer printers, and other peripheral devices, access needed data by performing direct memory access of a memory space. Memory size and processor power are significant factors in the cost of electronic devices, such as ink jet printers. In video-type applications, much of the data stored in memory is white space. For example, in a tri-color ink jet cartridge, some nozzles may be restrained from firing at various times during printing to compensate for the physical layout of the print cartridge. This is typically accomplished by placing zeros in a corresponding memory location in a print buffer for these nozzles. Not only does this waste memory space by filling the print buffer with zeros, but it also decreases processor bandwidth as direct memory access from an application specific integrated circuit (ASIC) interrupts processor operations. Large blocks of other types of repetitive data, such as all ones or repetitive patterns of data, also give rise to significant overhead in terms of both buffer size and processor bandwidth.
Therefore, there exists a need for a digital device that, when transferring data from one memory location to another, is capable of detecting blocks of repetitive data and generating the repetitive data without requiring memory access.
SUMMARY OF THE INVENTION
In one embodiment, the invention is directed to a system for reducing direct memory access (DMA) for ink jet control by indicating to a DMA controller when a large sequence of zeros is to be written to the ink jet. By doing so, the system dedicates less memory to printer control, as the zeros need not be stored in memory. Furthermore, the system saves time and memory bandwidth because the controller does not have to access memory while writing a large sequence of zeros.
The system avoids DMA while writing zeros by using a DMA controller that uses three memory access pointers: (1) a current address pointer, which points to the address of the word that is just about to be accessed; (2) an end segment pointer, which points to the address of the last word of the segment currently being accessed; and (3) a next segment pointer, which points to the first word of the next segment to be accessed. If the address of the current address pointer is invalid (at least with respect to DMA addresses), then the DMA controller will automatically write a word of zeros to the printer.
When a long sequence of zeros is about to be printed, the DMA controller indicates a transition from non-zero data to zero data by writing the last non-zero valid address of the segment currently being accessed to the end segment pointer and by writing an invalid address to the next segment pointer. When the DMA controller begins generating words of zeros, it writes to the end segment pointer a value equal to the first invalid address corresponding to the beginning of the sequence of zeros plus the number of zero words to be written and writes to the next segment pointer a valid address corresponding to the next address containing non-zero data.
In one aspect the invention is a method of reducing direct memory access in a machine employing a data segmenting scheme. Transfer of a repetitive block of data is detected. The repetitive block of data repeats a data word of a predetermined value. A first invalid address is assigned to a current address pointer. The first invalid address indicates that the repetitive block of data is to be generated. A second invalid address is assigned to an end segment pointer. The second invalid address corresponds to the first invalid address plus a value indicating a number of repetitive data words that is included in the block of repetitive data. While the current address pointer has a value assigned thereto that is not equal to the second invalid address, a data word of the predetermined value is generated and the value assigned to the current address pointer is stepped.
In another aspect of the invention, if a repetitive block of data is to be transferred, then a first invalid address is assigned to a next segment pointer. The first invalid address indicates that the repetitive block of data is to be generated after a transfer of a first data segment is complete. If non-repetitive data is to be transferred, a first memory address of a second data segment is assigned to the next segment pointer. When transfer of the first data segment is complete, a value currently assigned to the next segment pointer is assigned to a current address pointer.
While the value assigned to current address pointer corresponds to a valid memory address, a value corresponding to a last memory address of a second data segment is assigned to an end segment pointer. While the value assigned to the current address pointer is not equal to the value assigned to the end segment pointer, a memory location addressed at the value assigned to the current address pointer is accessed, a data word stored in the memory location is fetched, and the value assigned to the current address pointer is stepped.
While the value assigned to current address pointer corresponds to an invalid memory address, a value corresponding to the value assigned to the current address pointer plus the predetermined number of repetitions is assigned to an end segment pointer. While the value assigned to the current address pointer is not equal to the value assigned to the end segment pointer a data word of a predetermined type is generated and the value assigned to the current address pointer is stepped.
In yet another aspect, the invention is a printer that includes a printer controller having a digital control circuit programmed to detect when a repetitive block of data is to be printed, wherein the repetitive block of data repeats a data word of a predetermined value. The control circuit assigns a first invalid address to a next segment pointer, the first invalid address indicating that the repetitive block of data is to be generated after a transfer of a current segment is complete; assigns a second invalid address to an end segment pointer, the second invalid address corresponding to the first invalid address plus a value indicating a number of repetitive data words that is included in the block of repetitive data; and assigns the first invalid address to a current address pointer. While the current address pointer has a value assigned thereto that is less than the second invalid address, the printer controller generates a data word of the predetermined value and steps the value assigned to the current pointer. The printer also includes a printer mechanism that receives the data word of the predetermined value from the printer controller and that executes a print operation corresponding to the data word of predetermined value.
These and other aspects will become apparent from the following description of the preferred embodiment taken in conjunction with the following drawings, although variations and modifications may be effected without departing from the spirit and scope of the novel concepts of the disclosure.
REFERENCES:
patent: 4912632 (1990-03-01), Gach et al.
patent: 5077664 (1991-12-01), Taniai et al.
patent: 5212795 (1993-05-01), Hendry
patent: 5287471 (1994-02-01), Katayose et al.
patent: 5487138 (1996-01-01), Rust et al.
patent: 5579453 (1996-11-01), Lindenfelser et al.
patent: 5655151 (1997-08-01), Bowes et al.
patent: 5696989 (1997-12-01), Miura et al.
patent: 5765022 (1998-06-01), Kaiser et al.
patent: 5797033 (1998-08-01), Ecclesine
patent: 5805778 (1998-09-01), Suzuki
patent: 5828856 (1998-10-01), Bowes et al.
patent: 5828901 (1998-10-01), O'Toole et al.
patent: 5829054 (1998-10-01), Ehlig et al.
patent: 5835788 (1998-11-01), Blumer et al.
patent: 5857114 (1999-01-01), Kim
patent: 5983301 (1999-11-01), Baker et al.
patent: 6006286 (1999-12-01), Baker et al.
patent: 6081852 (2000-0
Chace Christian P.
Daspit Jacqueline M.
Kim Matthew
Lexmark International Inc.
Needle & Rosenberg P.C.
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