Electronic digital logic circuitry – Reliability – Redundant
Patent
1995-10-19
1997-01-07
Westin, Edward P.
Electronic digital logic circuitry
Reliability
Redundant
326 41, 326 38, 365200, H01L 2500
Patent
active
055921027
ABSTRACT:
A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
REFERENCES:
patent: Re33521 (1991-01-01), Mori et al.
patent: 3805039 (1974-04-01), Stiffler
patent: 3995261 (1976-11-01), Goldberg
patent: 4020469 (1977-04-01), Manning
patent: 4566102 (1986-01-01), Hefner
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4677318 (1987-06-01), Veenstra
patent: 4691301 (1987-09-01), Anderson
patent: 4706216 (1987-11-01), Carter
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4722084 (1988-01-01), Morton
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4798976 (1989-01-01), Curtin et al.
patent: 4800302 (1989-01-01), Marum
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 5019736 (1991-05-01), Furtek
patent: 5121006 (1992-06-01), Pedersen
patent: 5187393 (1993-02-01), El Gamal et al.
patent: 5204836 (1993-04-01), Reed
patent: 5220214 (1993-06-01), Pedersen
patent: 5255228 (1993-10-01), Hatta
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5325334 (1994-06-01), Roh
patent: 5369314 (1994-11-01), Patel et al.
patent: 5434514 (1995-07-01), Cliff
patent: 5459342 (1995-10-01), Nogami
patent: 5471427 (1995-11-01), Murakami
patent: 5485102 (1996-01-01), Cliff
patent: 5498975 (1996-03-01), Cliff
"A Survey of Microcellular Research," R. C. Minnick, Journal of the Association of Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967.
"Introducing Redundancy in Field Programmable Gate Array," F. Hatori, Proceedings of the IEEE 1993 Custom Integrated Circuits Conference held in San Diego California, 1993, pp. 7.1.1-7.1.4, May 9-12.
"Preliminary Data, Altera 32 Macrocell High Desity Max EPLD EPM 5032," 1988, Altera Corporation, Santa Clara (now San Jose), CA.
"Programmable Logic Arrays--Cheaper by the Millions," S. E. Wahlstrom, Electronics, Dec. 1967, pp. 90-95.
"Programmable Logic Devices with Spare Circuits for Use in Replacing Defective Circuits," 1988, Altera Corporation, San Jose, CA.
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422.
K. Kokkonen et al., "Redundancy Techniques for Fast Static RAMs,"Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 80-81, Feb., 1981.
J. Bindels et al., "Cost-Effective Yield Improvement in Fault-Tolerant VLSI Memory," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 82-83, Feb., 1981.
S. Eaton et al., "A 100ns 64K Dynamic RAM Using Redundancy Techniques," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 84-85, Feb., 1981.
Lane Christopher F.
Reddy Srinivas T.
Wang Bonnie I.
Altera Corporation
Jackson Robert R.
Sanders Andrew
Westin Edward P.
LandOfFree
Means and apparatus to minimize the effects of silicon processin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Means and apparatus to minimize the effects of silicon processin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Means and apparatus to minimize the effects of silicon processin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1767525