Maximum likelihood decoding method and information reproducing a

Details Maximum likelihood decoding method and information reproducing a Maximum likelihood decoding method and information reproducing a

Filed on

1996-11-13

Date issued

1999-08-17

Examiner

Grant, William

Patent Class

Error detection/correction and fault detection/recovery

SubClass

Pulse or data error handling

SubSubClass

Digital data error correction

Other Related Categories

371 432, 371 434, 371 437, 371 438, 371262, 371341, 371232, G06F 1110

Type

Patent

Status

active

Patent number

059387882

Description

ABSTRACT:
A Viterbi decoder corresponding to PR IV system is composed of an even signal sequence processing circuit and an odd signal sequence processing circuit. A branch metric calculating circuit calculates branch metrics with an amplitude reference level R. In each of expressions for calculating the branch metrics, the number of adding operations is described to one or less. By averaging the number of calculations, the calculation speed of branch metrics can be increased. Thus, the overall process speed of the decoder can be increased. In addition, with a limitation of which the LSB of the reference level R is fixed to "0", the bit width of data to be calculated can be decreased. As a result, the number of adders, registers, and so forth can be decreased.

REFERENCES:
patent: 4777636 (1988-10-01), Yamashita et al.
patent: 5095484 (1992-03-01), Karabed et al.
patent: 5327440 (1994-07-01), Fredrickson et al.
patent: 5432820 (1995-07-01), Sugawara et al.
Biver, M., et al. "In-Place Upadating of Path Metrics in Viterbi Dicoders", IEEE Jnl. Solid-State Circuits, vol. 24, No. 4, pp. 1158-1160, Aug. 1989.
Collins, "Decoding of Trellis Codes" IEEE, pp. 28-29, 1988.
Provence et al. "Systolic Arrays for Viterbi Processing in Communication Systems with a Time-Dispersive Channel", IEEE, pp. 1148-1156, Oct. 1988.

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