Maximum likelihood decoder and decoding method therefor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S794000, C369S059220

Reexamination Certificate

active

07937650

ABSTRACT:
According to one embodiment, a maximum likelihood decoder includes a branch metric calculator, a processor configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric memory, and outputs a selection signal for identifying a selection result, a path memory configured to store a time variation of the selection signal, and a path detection module configured to detect a decoding signal based on the time variation of the stored selection signal. A decoding method includes selecting operation modes of at least one of the branch metric calculator, the processor, and the path memory between a first operation mode in which an operation is performed at a channel rate frequency and a second operation mode in which an operation is performed at a specific frequency lower than the channel rate frequency.

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Notice of Reason for Rejection mailed Aug. 11, 2009, from the Japanese Patent Office for Japanese Patent Application No. 2008-164946 (2 pages).

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