Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1996-11-01
2001-11-06
Malinowski, Walter J. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S038000, C349S192000
Reexamination Certificate
active
06313889
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a matrix-type display device, and more particularly, to a matrix-type display which can be repaired in a pixel unit.
As an interface between a person and a computer, there are provided various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), electroluminesence (EL) and field emission display (FPD), instead of a conventional cathode ray tube (CRT). These flat panel display devices adopt a matrix-type wiring layout in which horizontal and vertical signal lines cross at right angles. This matrix-type wiring layout will be described with reference to the appended drawings.
FIG. 1
is a plan view showing the layout of a matrix-type display device.
As shown in
FIG. 1
, in the conventional matrix-type display device, a plurality of scanning signal lines G
1
, G
2
, . . . , G
m
are parallel formed in the horizontal direction and a plurality of displaying signal lines D
1
, D
2
, D
3
, D
4
, . . . , D
2n−1
and D
2n
are formed in the vertical direction, which crosses with the scanning signal lines while an insulating layer is interposed therebetween.
Each end of the scanning signal lines G
1
, G
2
, . . . , G
m
has input pads GP
1
, GP
2
, . . . , GP
m
to which signals are input, and each end of the displaying signals lines D
1
, D
2
, D
3
, D
4
, . . . , D
2n−1
and D
2n
also has input pads DP
1
, DP
2
, DP
3
, DP
4
, . . . , DP
2n−1
and DP
2n
. Here, the input pads of the displaying signal lines D
1
, D
3
, . . . and D
2n−1
are formed at upper part of the matrix wiring layout, and the displaying signal lines D
2
, D
4
, . . . and D
2n
have the input pads which are formed at bottom part of the wiring layout.
On the other hand, a pixel (PX) is formed in each space formed by the cross of the scanning signal lines G
1
, G
2
, . . . , G
m
and the displaying signal lines D
1
, D
2
, D
3
, D
4
, . . . , D
2n−1
and D
2n
, with a matrix arrangement. Here, the layout of the pixel may vary according to the type of the display device.
The LCD as one of the flat panel display devices which have been highlighted recently adopts an electro-optical effect of a liquid crystal material. The driving mode of the LCD is roughly classified into a simple matrix type and an active matrix type.
According to the active matrix type LCD, a switching clement having a non-linear characteristic is appended to each pixel with the matrix arrangement to control the operation of each pixel. Here, a thin film transistor (TFT) of three-terminals type is generally used as the switching element and a thin film diode (TFD) such as a metal insulator metal (MIM) of two-terminals type may be used for the switching element.
Especially, the LCD adopting a TFT as the switching element is comprised of a TFT, a pixel electrode, a TFT substrate on which scanning signal lines or gate lines for supplying a scanning signal or a switching signal and displaying signal lines or data lines for supplying a displaying signal or an image signal are formed, an opposing substrate on which a common electrode is formed, and a liquid crystal material which is injected between the TFT substrate and the opposing substrate.
Hereinafter, the pixel layout of the TFT-LCD will be described with reference to FIG.
2
.
FIG. 2
is a diagram showing a conventional TFT-LCD. Each pixel (PX) includes a TFT formed on a lower substrate (TFT substrate), a liquid crystal capacitor (C
lc
) comprised of a pixel electrode
10
as a lower substrate, a common electrode (CE) as an opposing upper substrate and a liquid crystal material filled between two electrodes, and a storage capacitor (C
st
) formed on the lower substrate. Here, the storage capacitor (C
st
) stores a signal applied to the pixel PX for a predetermined time lapse. On the other hand, the pixel PX is connected to a data line and a gate line via the TFT. For example, three terminals of the TFT are connected to the data line, the gate line and the pixel electrode
10
, respectively. However, in
FIG. 2
, the TFT for switching a corresponding pixel (PX) exists outside the pixel, that is, a terminal of the TFT is connected to a pixel electrode of the adjacent pixel to drive the adjacent pixel. On the contrary, a TFT for driving a pixel may be formed in the corresponding pixel.
The display operation of the LCD is as follows. A predetermined voltage or a periodic voltage is applied to the common electrode CE, and a voltage is applied to the pixel electrode
10
via the TFT. Consequently, the display operation is performed by the electro-optical effect of the liquid crystal material composing the liquid crystal capacitor C
lc
.
Referring to
FIGS. 3 and 4
, the plan layout and the vertical layout of the TFT substrate corresponding to the lower substrate of the LCD having the layout as shown in
FIGS. 1 and 2
will be described.
FIG. 3
is a plan view showing the layout of the TFT substrate corresponding to the lower substrate of the LCD shown in FIG.
2
. Here, the gate line has an layout of a closed curve enclosing the pixel electrode.
FIG. 4
is a sectional view of a portion cut along a line A—A shown in FIG.
3
. Here, the regions represented by PX
i
(i=1, 2, 3, 4), having a rectangular-like form, correspond to the lower portion of a pixel. For convenience' sake, let's call the rectangular-like regions including the gate line and the data line as “pixel” or “pixel region.” Also, let's call a set of pixels formed in the horizontal direction and a set of pixels formed in the vertical direction as “pixel row” and “pixel column”, respectively.
As shown in
FIGS. 3 and 4
, the upper and lower gate lines G
up
and G
down
are formed on a transparent insulating substrate above and below a pixel row. The lower gate line G
down
extends straight in the horizontal direction. The upper gate line G
up
is comprised of a first horizontal portion G
h1
which is the longest portion thereof, a first vertical portion G
v1
extending downward from the end of the first horizontal portion G
h1
, a second horizontal portion G
h2
extending in the horizontal direction from the end of the first vertical portion G
v1
, and a second vertical portion G
v2
extending upward from the end of the second horizontal portion G
h2
. This layout of the upper gate line G
up
is duplicated with respect to each pixel. Generally, the above dual layout of the gate line called a dual gate line layout.
The first horizontal portion G
h1
of the upper gate line G
up
and the lower gate line G
down
are connected by a left auxiliary gate line
1
a
, and the second vertical portion G
v2
of the upper gate line G
up
is lengthened downward to form a right auxiliary gate line
1
b
reaching the lower gate line G
down
.
A data line D is vertically formed between each pixel column and crosses with the first horizontal portion G
h1
of the upper gate line G
up
and the lower gate line G
down
via an gate insulating layer
4
(see FIG.
4
).
The upper and lower gate lines G
up
and G
down
and a pair of left and right auxiliary gate lines
1
a
and
1
b
form a closed curve as a black matrix. In the region defined by the closed curve, there is formed the pixel electrode
10
with which the gate lines G
up
and G
down
and the auxiliary gate lines
1
a
and
1
b
are overlapped while the gate insulating layer
4
(see
FIG. 4
) and a protection layer
9
(see
FIG. 4
) which will be described later are interposed between the pixel electrode
10
and gate lines G
up
and G
down
and the auxiliary gate lines
1
a
and
1
b
. Here, the overlapped portion plays as the storage capacitor C
st
(see FIG.
2
). This storage capacitor formed in a closed curve is called “ring capacitor.” Also, only the upper and lower gate lines G
up
and G
down
and the auxiliary gate lines
1
a
and
1
b
forming the ring capacitor may call a ring capacitor for short. Here, a ring capacitor means the latter.
It is preferable that the gate lines G
up
and G
down
and the auxiliary gate lines
1
a
and
1
b
have the
Kim Dong-gyu
Kim Kyung-Seop
Kim Shi-Yual
Lee Jung-Hee
Lee Kyung-Nam
Jones Volentine, L.L.C.
Malinowski Walter J.
Samsung Electronics Co,. Ltd.
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