Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-09
2005-08-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06928634
ABSTRACT:
A method for performing a matrix-based verification technique such as optical process correction (OPC) that analyzes interactions between movement of a fragment on a mask and one or more edges to be created on a wafer. In one embodiment, each edge to be created is analyzed and one or more fragments of a mask are moved in accordance with a gradient matrix that defines how changes in position of a fragment affect one or more edges on the mask. Fragments are moved having a significant effect on an edge in question. Simulations are performed and fragments are moved in an iterative fashion until each edge has a objective within a prescribed tolerance. In another embodiment, each edge has two or more objectives to be optimized. A objective is selected in accordance with a cost function and fragments are moved in a mask layout until each edge has acceptable specification for each objective.
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Cobb Nicolas
Granik Yuri
Christensen O'Connor Johnson & Kindness PLLC
Levin Naum
Siek Vuthe
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