Matrix memory with redundancy and minimizes delay

Details Matrix memory with redundancy and minimizes delay Matrix memory with redundancy and minimizes delay

1989-12-20

1991-07-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

365200, 36523003, G11C 1300

Patent

active

050330241

ABSTRACT:
An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.

REFERENCES:
patent: 4599709 (1986-07-01), Clemons

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