Matrix decoder

Details Matrix decoder Matrix decoder

2006-09-19

2010-10-26

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S106000, C326S108000

Reexamination Certificate

active

07821299

ABSTRACT:
A matrix decoder is provided, which includes a plurality of first level shifters, a plurality of second level shifters, and a demultiplexer. The first level shifters and the second level shifters boost the voltages of inputted signals to the voltages required by high voltage components and output the boosted signals. One of the first level shifters receives a first logic state and outputs a fifth logic state. Each of the other first level shifters receives a second logic state and outputs a sixth logic state. One of the second level shifters receives a third logic state and outputs a seventh logic state. Each of the other second level shifters receives a fourth logic state and outputs an eighth logic state. The demultiplexer outputs a ninth logic state and a plurality of tenth logic states according to the logic states outputted by the first level shifters and the second level shifters.

REFERENCES:
patent: 4344005 (1982-08-01), Stewart
patent: 2010/0007643 (2010-01-01), Wu et al.
Rhyne, Fundamentals of Digital Systems Design, N.J., 1973, pp. 70-71.

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