Matrix arithmetic circuit

Details Matrix arithmetic circuit Matrix arithmetic circuit

1993-08-05

1994-03-29

Nguyen, Long T.

Boots, shoes, and leggings

3647505, 364758, G06F 752, G06F 738

Patent

active

052991466

ABSTRACT:
A matrix arithmetic circuit includes an address generator, a first multiplier, a second multiplier, and an accumulator. The address generator generates addresses of first, second, and third memories to read out matrix elements from the first, second, and third memories at predetermined timings. The first multiplier multiplies the first and second matrices. The second multiplier multiplies the multiplication result from the first multiplier and the third matrix. The accumulator accumulates the multiplication result from the second multiplier to obtain an arithmetic result.

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patent: 4719588 (1988-01-01), Tatemichi et al.
patent: 4819155 (1989-04-01), Wulf et al.
patent: 4841469 (1989-06-01), Kuenemund et al.
patent: 4852037 (1989-07-01), Aoki
patent: 5021987 (1991-07-01), Chan et al.
Leung, S. S., et al., "Real-Time Direct Kinematics on a VLSI Chip," Proceedings of a Real-Time System Symposium, IEEE Computer Society Press, New York, U.S., Dec. 2, 1986, pp. 257-263.
"A Single-Chip 16-bit 25-ns Real-Time Video/Image Signal Processor", by Kouichi Kikuchi et al., IEEE Journal of Solid-State Circuits vol. 24, No. 6, Dec. 1989, pp. 1662-1667.

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