Materials and methods for sublithographic patterning of gate...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S780000, C430S312000, C430S313000

Reexamination Certificate

active

06884735

ABSTRACT:
An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist layer after provision of the hydrophilic layer. The diffusion can lead to plasticization of the photoresist layer polymers in exposed regions relative to unexposed regions. The process can be utilized to form a large variety of integrated circuit structures including gate structures and other features with wide process latitude and smooth feature side walls.

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