Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-04-26
2005-04-26
Blum, David S. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S780000, C430S312000, C430S313000
Reexamination Certificate
active
06884735
ABSTRACT:
An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist layer after provision of the hydrophilic layer. The diffusion can lead to plasticization of the photoresist layer polymers in exposed regions relative to unexposed regions. The process can be utilized to form a large variety of integrated circuit structures including gate structures and other features with wide process latitude and smooth feature side walls.
REFERENCES:
patent: 5487967 (1996-01-01), Hutton et al.
patent: 5585215 (1996-12-01), Ong et al.
patent: 6132928 (2000-10-01), Tanabe et al.
patent: 6316159 (2001-11-01), Chang et al.
patent: 6319853 (2001-11-01), Isibashi et al.
patent: 6436593 (2002-08-01), Minegishi et al.
patent: 6461784 (2002-10-01), Komine et al.
patent: 6472120 (2002-10-01), Jung et al.
patent: 6596200 (2003-07-01), Ogawa et al.
patent: 6716571 (2004-04-01), Gabriel et al.
patent: 6720132 (2004-04-01), Tsai et al.
patent: 6743572 (2004-06-01), Richter et al.
M. Siebald, R. Sezi, R. Leuscher, H. Ahne, S. Birkle,Proc. SPIE, 528 (1990). 12 pgs.
M. Siebald, R. Sezi, R. Leuscher, H. Ahne, S. Birkle,Microelectronic Engineering, 531 (1990) 6 pgs.
M. Siebald, J. Berthold, M. Beyer, R. Leuscher, Ch. Nolsher, U. Scheler, R. Sezi,Proc. SPIE, 1446, paper 21 (1991). 13 pgs.
R. Leuscher, M. Beyer, H. Bomforder, E. Kuhn, Ch. Nolscher, M. Siebald, R. Sezi,Proc. Soc. Plastic Engineers, Mid-Hudson Section, Regional Technical Conference, 215, Oct. (1991). 12 pgs.
Acheta Alden
Okoroanyanwu Uzodinma
Advanced Micro Devices , Inc.
Blum David S.
Foley & Lardner LLP
LandOfFree
Materials and methods for sublithographic patterning of gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Materials and methods for sublithographic patterning of gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Materials and methods for sublithographic patterning of gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3407001