Materials and method to seal vias in silicon substrates

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S643000, C257S647000, C257SE21546, C257SE21553, C257SE21585

Reexamination Certificate

active

10908480

ABSTRACT:
Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

REFERENCES:
patent: 5904502 (1999-05-01), Ference
patent: 5998292 (1999-12-01), Black et al.
patent: 6593644 (2003-07-01), Chiu et al.
patent: 6740931 (2004-05-01), Kouzuki et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Materials and method to seal vias in silicon substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Materials and method to seal vias in silicon substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Materials and method to seal vias in silicon substrates will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3773220

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.