Material deposition from a liquefied gas solution

Details Material deposition from a liquefied gas solution Material deposition from a liquefied gas solution

2002-01-02

2004-01-13

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S643000, C438S687000, C438S677000, C438S678000, C438S680000, C438S684000, C438S745000

Reexamination Certificate

active

06677233

ABSTRACT:

BACKGROUND
The present invention relates to semiconductor fabrication. In particular, the present invention relates to semiconductor processing feature deposition methods.
BACKGROUND OF THE RELATED ART
In the fabrication of semiconductor devices, materials of varying purposes are deposited on a semiconductor substrate. For example, a metal layer can be deposited on a patterned substrate to form capacitor features such as parallel metal lines. The patterned substrate will include trenches to accommodate the metal lines.
A barrier layer is often first formed on the patterned substrate and within the trenches to prevent diffusion of metal ions into the substrate. For example, where copper (Cu) metal lines are to be formed in the trenches, a barrier layer of tantalum (Ta) can first be deposited to prevent copper ions (e.g. Cu
+
) from diffusing beyond the trenches into the substrate and compromising performance of the semiconductor device. The copper (Cu) can then be deposited above the tantalum (Ta) barrier. Deposition may proceed by, for example, a physical vapor depositon (PVD) process, a chemical vapor deposition (CVD) process or a plasma enhanced CVD (e.g. PECVD) process.
Where a barrier layer is deposited as described above, oxidation occurs on the surface of the barrier layer as it is exposed to air. This generally occurs as the substrate is transferred from a barrier deposition reactor to another reactor for deposition of the metal layer. Unfortunately, the metal to be deposited does not adhere as well to the barrier layer once it has been oxidized. Therefore, to ensure better adherence between the metal and barrier layers, added measures are often taken prior to complete metal layer deposition. For example, a seed layer of the metal to be deposited is generally deposited above the barrier layer including within the narrow trenches. The thin seed layer is fairly uniform and continuous. The seed layer can be deposited by a physical vapor deposition (PVD) process. The formation of an initial seed layer prior to complete metal layer deposition increases, to a limited extent, the adherence between the barrier layer and the fully deposited metal layer. However, adding a seed layer requires additional time and expense, decreasing the overall efficiency of semiconductor processing.
In addition to decreased efficiency, the degree of uniformity in thickness of the seed layer described above is limited. Unfortunately, in a trench to be filled completely by a metal, a non-uniform seed layer can lead to occlusion of the trench. For example, where thicker portions of the seed layer from opposing walls of the trench come in contact with one another (or close to one another), the trench can be precluded from adequate metal deposition there below leaving trapped voids. Thicker seed layer portions are near the top, step portion, of the trench. These thicker portions of the seed layer are generally referred to as “overhang”. As trenches become smaller and smaller, with trench walls coming closer and closer together, the problem of overhang becomes even more pronounced.
It is possible for surface oxides to be dissolved and use of a seed layer avoided for purposes of adhesion. However, deposition of the entire metal layer directly on the barrier layer by conventional methods, such as CVD or PECVD, does not naturally occur in a ‘bottom up’ (super-fill) manner. That is, conventional deposition methods fail to ensure that the metal layer is formed from the bottom of the trench up. Therefore, the likelihood of trapped voids and inadequate metal layer formation remains.


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Wolf and Tauber, “Silicon Processing for the VLSI era”, vol. 1 Process Technology, pp. 516-517.*
Wolf and Tauber, “Silicon Processing for the VLSI era”, vol. 2 Process Technology, pp. 256-257, 260.*
Search Report for PCT/US 02/41705, mailed Jun. 11, 2003, 4 pages.

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