Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-04-26
2001-07-10
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185200, C365S185210, C365S230030
Reexamination Certificate
active
06259645
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a memory integrated circuit. More particularly, the present invention relates to a method and apparatus for matching the loading on a sensing reference circuit and a selected memory cell in a dual bank flash memory integrated circuit.
Memory circuits such as flash memory circuits conventionally include an array of memory cells, address decoding circuits for selecting one or more memory cells in the array, and a sensing circuit for sensing the data state of the selected memory cell. The sensing circuit compares a sensed signal, such as a voltage or current, from the selected memory cell with an analogous signal from a reference cell. Based on this comparison, the sensing circuit determines if the selected memory cell stores a logic 1 or a logic 0. The proper data is then provided to an output buffer for communication off-chip.
The sensing circuit must be very sensitive to detect the sensed signal. The node conveying sensed signal coming from a memory cell to the sensing circuit may travel the length of the integrated circuit. This node is referred to as a data line. The data line may include sources or drains of a large number of transistors, for example, in the address decoding circuit. The length of the data line and the other components connected to the data line introduce a large amount of capacitance and resistance on the data line. This introduces a non-zero RC time constant which slows the sensing of the signal on the data line.
To optimize the performance of the sensing circuit, it is known to balance the load on the sensed signal and the reference signal. The reference circuit may be positioned anywhere on the integrated circuit, either close to the sensing circuit or far away. The sensing circuit's performance is improved when the RC time constant of the reference circuit matches the RC time constant of the data line. This has been done, for example, by putting dummy metal lines on the chip to simulate capacitance on the bit line or data line being sensed. Also, transistors matching those on the data line have been electrically coupled to the reference line to further match the capacitive load. This technique has produced good results.
A new type of memory integrated circuit includes two independent banks of memory cells. In this architecture, a user can write a memory cell in a first bank while simultaneously reading a memory cell in the second bank. The enhances the flexibility of the memory chip for the user.
However, if two banks are not of the same size, separate matching circuits become necessary for the first bank and the second bank of memory cells. The RC load seen on bit lines and data lines in the two banks is largely dependent on the physical size of the bank and the number of transistors coupled to the bit lines and the data lines. To match the loading for each bank at the reference circuit, two loading circuits are necessary, one for each bank.
However, duplicating circuits is contrary to some of the basic design goals of integrated circuit design. These include minimizing the number of devices on the chip and minimizing chip size. Minimizing chip size is important because the manufacturing cost of the integrated circuit is directly related to the size of the chip. Minimizing the number of devices on the chip is important because each device increases the size of the chip, each device is a possible source of failure of the chip, and each device, when active, adds to the overall current drain of the chip. Minimizing current drain to produce a low power design is another basic design goal of integrated circuit design.
Accordingly, there is a need for a method and apparatus which permit accurate matching of the loading on a reference memory cell of a dual bank memory chip.
BRIEF SUMMARY OF THE INVENTION
By way of introduction only, a dual bank memory integrated circuit in accordance with the embodiments illustrated herein includes a single loading circuit. When a first bank of the dual bank chip is accessed, first loading circuitry is coupled to a reference core cell. A sensing circuit compares the signal from the selected memory cell with a signal from the reference core cell. When a second bank of the dual bank chip is accessed, second loading circuitry is also coupled to the reference core cell, along with the first loading circuitry. Thus, the first loading circuitry is used for balancing during an access of either the first bank or the second bank. The second loading circuitry is added only during an access of the second bank. This allows the devices required for load matching to be re-used, reducing the chip area required for the loading circuit and reducing the current drain of the overall integrated circuit.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation of the following claims, which define the scope of the invention.
REFERENCES:
patent: 5850366 (1998-12-01), Coleman, Jr.
patent: 5901086 (1999-05-01), Wang et al.
patent: 6038169 (2000-03-01), Ogura et al.
patent: 6052308 (2000-04-01), Pitts
patent: 6078518 (2000-06-01), Chevallier
patent: 6128227 (2000-10-01), Kim
Chen Tien-Min
Shieh Ming-Huei
Advanced Micro Devices , Inc.
Brinks Hofer Gilson & Lione
Hoang Huan
LandOfFree
Matching loading between sensing reference and memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Matching loading between sensing reference and memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Matching loading between sensing reference and memory cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2455684