Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For high frequency device
Reexamination Certificate
2002-06-14
2003-11-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For high frequency device
C257S786000, C257S691000
Reexamination Certificate
active
06646343
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a package for an integrated circuit. In particular, the present invention relates to techniques for wire-bonding of electrical connections between leads of an integrated circuit package and a high-speed integrated circuit formed on a semiconductor substrate.
DISCUSSION OF THE RELATED ARTS
An integrated circuit typically includes a plastic or ceramic package that encapsulates an electronic circuit formed on a semiconductor substrate (“semiconductor die”). Typically, terminals are provided on the package for external connections. In one type of package, known as a “ball grid array” (BGA) package, the external terminals provide solder balls which can be bonded onto conductive traces on a printed circuit board for connection to other circuit elements provided on the printed circuit board.
FIG. 1
shows a cross section of “cavity down” BGA package
100
, which includes semiconductor die
101
provided in cavity
108
, multi-layer circuit board
102
, solder balls
103
and bond wires
104
. Multi-layer circuit board
102
includes a number of conductor layers insulated from each other by one or more layers of dielectric material. The conductor layers are each patterned to route a signal or a reference potential to an external terminal provided by solder balls
103
. As shown in
FIG. 1
, bond wires
104
connect the conductor traces on multi-layer circuit board
102
to semiconductor die
101
's bonding pads, which are input and output ports of an electronic circuit fabricated on semiconductor die
101
. The conductor traces are conductors etched or laminated on different layers of insulators in multi-layer circuit board
102
. These conductor traces are connected to other layers of conductor traces and solder balls
103
by vias
105
.
In a high-speed integrated circuit, such as one operating at the 10 gigahertz (10 GHz) range, the complex impedance (e.g., inductance) introduced by bond wires can significantly affect signal quality by distorting signal waveforms and introducing noise. It is believed that a conventional wire-bonded BGA package cannot support a 1 GHz integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides a method and an integrated circuit package that can support a high-speed integrated circuit operating at 10 GHz or higher switching speeds.
According to one embodiment of the present invention, a packaged integrated circuit having external terminals is provided a semiconductor die having conventional bonding pads, a substrate (e.g., printed circuit board) having conductive traces to couple input, output or bi-directional signals between bonding finger areas of the conductive traces and the external terminals. In one embodiment, a ground plate that is electrically isolated from a conductive trace is positioned in the vicinity of the bonding finger area of the conductive trace. Bond wires connect the bonding pads of the electronic circuit and the bonding finger areas of the conductive traces. The ground plate improves integrity in a high-speed signal by canceling the complex impedance of a bond wire.
According to another aspect of the invention, a packaged integrated circuit of the present invention can use two or more bond wires to connect the same bonding finger area of a conductive trace on the substrate and a corresponding bonding pad of the electronic circuit. In one embodiment, the packaged integrated circuit is a ball grid array package, which includes a multi-layer circuit board. The multiple bond wire approach reduces inductance in the bond wires.
In one embodiment of the present invention, a second conductive trace is provided adjacent the first conductive trace, so as to allow the first and second conductive traces to carry a differential signal to and from the electronic circuit. In that embodiment, a third conductive trace is provided on the substrate for receiving a reference signal, the third conductive trace being provided to substantially shield the first and second conductive traces.
REFERENCES:
patent: 4891686 (1990-01-01), Krausse, III
patent: 6064113 (2000-05-01), Kirkman
patent: 6437669 (2002-08-01), Welstand et al.
patent: 6538336 (2003-03-01), Secker et al.
Chen Jason
Gong Ge
Sharma Nirmal
BitBlitz Communications, Inc.
Ho Tu-Tu
Kwok Edward C.
MacPherson Kwok & Chen & Heid LLP
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