Match register with duplicate decoders

Electronic digital logic circuitry – Multifunctional or programmable – Array

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326 41, H03K 1977

Patent

active

057986568

ABSTRACT:
An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.

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