Master slave latch circuit with race prevention

Details Master slave latch circuit with race prevention Master slave latch circuit with race prevention

1986-11-13

1989-06-20

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307445, 307480, H03K 3284, H03K 1716, H03K 1902

Patent

active

048411680

ABSTRACT:
A master slave latch circuit is formed by a master latch circuit for outputting a master output signal and a slave latch circuit for outputting a slave output signal. A latch gate of the master latch circuit is formed so that it uses a data gate in common with the slave latch circuit. Accordingly, racing can be avoided and the number of gates can be reduced, and thus the advantage of an increase in the density of the circuit can be obtained.

REFERENCES:
patent: 3588545 (1971-05-01), Wright
patent: 4554465 (1985-11-01), Koike
patent: 4675553 (1987-05-01), Price et al.
Patent Abstracts of Japan, vol. 6, No. 28 (E-95), [906], Feb. 19, 1982; & JP-A-56 149 114 (Nippon Denki K.K.), 11-18-81.
IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6692, 6693; J. C. St. Clair, "Scannable Flip-Flops for CMOS LSI".

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