Master-slave delay locked loop for accurate delay or non-periodi

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327141, 395552, 395881, H04L7/00

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active

059053917

ABSTRACT:
The present invention involves an electrical component interface system. The system includes clocking circuitry to provide a clock signal. A sending component provide a non-periodic strobe signal and a data signal responsive to the clocking signal. A receiving component receives the strobe signal and data signal. The receiving component includes delay circuitry to delay the strobe signal so as to position edges of the strobe signal with respect to data cells of the data signal. The delay circuitry includes a loaded delay elements and DC level restoration circuitry to control the load of the loaded delay element. The delay elements may be a series of inverters loaded with RC loads. The DC level restoration circuitry may be pulse generation circuitry.

REFERENCES:
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patent: 5748018 (1998-05-01), Ishikawa
patent: 5794020 (1998-08-01), Tanaka et al.
Bazes, Mel and Roni Ashuri, "A Novel CMOS Digital Clock and Data Decoder", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1934-1940.
Lee, Thomas H. et al., "A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM", IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.
Reese, Edmund A. et al., A Phase-Tolerant 3.8 GB/s Data-Communication Router for a Multiprocessor Supercomputer Backplane, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1994, ISSCC94, pp. 296-297; and 1994 ISSCC Slide Supplement pp. 232-233, and 326-328.

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