Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1999-12-17
2001-07-03
Lefkowitz, Sumati (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S120000, C710S120000
Reexamination Certificate
active
06256693
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
The present invention is related to the field of processing systems, and more particularly to buses used in processing systems to interconnect a processor with other devices.
In processing systems, it is necessary for a processor to communicate with other system elements such as memory, control/status registers, peripheral devices, etc. It is common to employ a “bus”, or shared multi-wire connections, as a communications transport mechanism for such purposes.
There are certain features of known buses that are advantageous in certain kinds of processing systems. For example, buses intended for widespread use by different vendors have relatively complex signaling and data transfer mechanisms, in order to support a variety of types of devices and/or processors. Also, buses commonly provide for data transfer in different directions at different times, necessitating the use of bidirectional bus interface logic at some or all connection points to the bus. Bidirectional buses are especially useful for communication among different physical devices such as different integrated circuits, which have a limited number of package pins.
However, the above characteristics of known buses can be disadvantageous in other environments. In a complex integrated circuit (IC) having an on-chip bus, for example, the use of complex bus protocols and bidirectional data transfer make it difficult to verify the correctness of the IC design, and can also impair testability during manufacture. Accordingly, there is a need for a bus that is particularly suitable for on-chip use, and which avoids reliance on bidirectional data transfer.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a bus protocol and associated logic are disclosed that improve both the verifiability and testability of integrated circuits in which the bus is used. The bus employs unidirectional point-to-point connections rather than bidirectional connections, which further improves testability and also improves performance.
The disclosed bus has unidirectional address lines for carrying address signals from a single bus master to one or more bus slaves. The bus also has unidirectional data lines for carrying data from the master to the slaves, and unidirectional data lines for receiving data from the slaves. The master initiates a bus transaction by asserting a request signal while placing the address for the transaction on the address lines. A slave device responds to the request by returning an acknowledge signal. The master maintains the address and the request on the bus until a predetermined time after the acknowledge signal is received. For a read, the data is returned at a predetermined time after the acknowledge signal is received. For a write, the master places the write data on the outgoing data lines and maintains the data value on the bus until a predetermined time after the acknowledge signal is received. In one embodiment, the predetermined times are measured in clock cycles, so that there are no special asynchronous timing requirements for proper bus operation. Additionally, the master deasserts the request signal for at least one cycle between bus transactions, which enables the design of slave interface logic to be simplified.
Logic interfacing to the bus operates straightforwardly, due to the use of predetermined timing relationships in the signalling and the use of unidirectional rather than bidirectional connections. There are only a small number of operations to be tested, and each one follows a predictable pattern. Proper operation can be readily verified during the design phase and tested during manufacturing.
Other aspects, features and advantages of the present invention will be apparent from the detailed description below.
REFERENCES:
patent: 4339793 (1982-07-01), Marenin
patent: 4378589 (1983-03-01), Finnegan et al.
patent: 4547879 (1985-10-01), Hamelin et al.
patent: 4947316 (1990-08-01), Fisk et al.
patent: 5729703 (1998-03-01), Onn et al.
IBM Technical Disclosure Bulletin, “Chiplets'Interconnections Pathway Control and Merging of Master and Slaves Buses”, vol. 38, No. 06 Jun. 1995, pp. 375-377.
3Com Corporation
Lefkowitz Sumati
Weingarten, Schurgin Gagnebin & Hayes LLP
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