Master image chip organization technique or method

Details Master image chip organization technique or method Master image chip organization technique or method

1978-12-29

1981-10-13

Wojciechowicz, Edward J.

357 40, 357 46, 357 51, 357 55, 357 68, 357 71, H01L 2710

Patent

active

042951496

ABSTRACT:
Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions.
In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

REFERENCES:
patent: 4234888 (1980-11-01), Calhoun et al.
patent: 4249193 (1981-02-01), Balyoz et al.

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