Massively parallel processing system using two data paths: one c

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395858, G06G 1300

Patent

active

058647384

ABSTRACT:
A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.

REFERENCES:
patent: Re28577 (1975-10-01), Schmidt
patent: 4330858 (1982-05-01), Choquet
patent: 4630259 (1986-12-01), Larson et al.
patent: 4771391 (1988-09-01), Blasbalg
patent: 4868818 (1989-09-01), Madan et al.
patent: 4933933 (1990-06-01), Dally et al.
patent: 4965793 (1990-10-01), Polzin et al.
patent: 4974143 (1990-11-01), Yamada
patent: 4980852 (1990-12-01), Giroir et al.
patent: 4987537 (1991-01-01), Kawata
patent: 4995056 (1991-02-01), Fogg et al.
patent: 5008882 (1991-04-01), Peterson et al.
patent: 5027330 (1991-06-01), Miller
patent: 5031211 (1991-07-01), Nagai et al.
patent: 5036459 (1991-07-01), den Hann et al.
patent: 5068784 (1991-11-01), Kishino et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5157692 (1992-10-01), Horie et al.
patent: 5161156 (1992-11-01), Baum et al.
patent: 5170482 (1992-12-01), Shu et al.
patent: 5175733 (1992-12-01), Nugent
patent: 5195100 (1993-03-01), Katz et al.
patent: 5218601 (1993-06-01), Chujo et al.
patent: 5218676 (1993-06-01), Ben-Ayed et al.
patent: 5233618 (1993-08-01), Glider et al.
patent: 5239545 (1993-08-01), Buchholz
patent: 5274799 (1993-12-01), Brant et al.
patent: 5276899 (1994-01-01), Neches
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5303244 (1994-04-01), Watson
patent: 5313628 (1994-05-01), Medelsohn et al.
patent: 5313645 (1994-05-01), Rolfe
patent: 5331631 (1994-07-01), Teraslinna
patent: 5333279 (1994-07-01), Dunning
patent: 5341504 (1994-08-01), Mori et al.
patent: 5345565 (1994-09-01), Jibbe et al.
patent: 5347450 (1994-09-01), Nugent
patent: 5353283 (1994-10-01), Tsuchiya
patent: 5365228 (1994-11-01), Childs et al.
patent: 5394528 (1995-02-01), Kobayashi et al.
patent: 5402428 (1995-03-01), Kakuta et al.
patent: 5412782 (1995-05-01), Hausman et al.
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5440547 (1995-08-01), Easki et al.
patent: 5452444 (1995-09-01), Solomon et al.
patent: 5499377 (1996-03-01), Gordon
patent: 5513192 (1996-04-01), Janku et al.
patent: 5517497 (1996-05-01), LeBoudec et al.
patent: 5519844 (1996-05-01), Stallmo
patent: 5522031 (1996-05-01), Ellis et al.
patent: 5530948 (1996-06-01), Islam
patent: 5546549 (1996-08-01), Barrett et al.
patent: 5548639 (1996-08-01), Ogura et al.
patent: 5555524 (1996-09-01), Ogura et al.
patent: 5555542 (1996-09-01), Shiojiri et al.
patent: 5566321 (1996-10-01), Pase et al.
patent: 5574849 (1996-11-01), Sonnier et al.
patent: 5581705 (1996-12-01), Passint et al.
patent: 5627986 (1997-05-01), Frankland
"Deadlock-Free Routing Schemes on Multistage Interconnection Networks", IBM Technical Disclosure Bulletin, 35, pp. 232-233, (Dec., 1992).
"IEEE Standard for Scalable Coherent Interface (SCI)", IEEE Std 1596-1992, pp. 1-248 (Mar., 1992).
"Message Routing Systems for Transputer-Based Multicomputers", IEEE Micro, Jun. 13, 1993, No. 3, Los Alamitos, CA.
Adve, V.S., et al., "Performance Analysis of Mesh Interconnection Networks with Deterministic Routing", Transactions on Parallel and Distributed Systems, pp. 225-246, (Mar., 1994).
Bolding, K., "Non-Uniformities Introduced by Virtual Channel Deadlock Prevention", Technical Report 92-07-07, Department of Computer Science and Engineering, FR-35 University of Washington; Seattle, WA 98195, (Jul. 21, 1992).
Bolla, F.R., "A Neural Strategy for Optimal Multiplexing of Circuit-And Packet-Switched Traffic", Department of Communications, Computer and Systems Science (DIST), University of Genoa, pp. 1324-1330.
Boura, Y.M., et al., "Efficient Fully Adaptive Wormhole Routing in n-dimensional Meshes", IEEE, pp. 589-596, (Jun. 21, 1994).
Bundy, A., et al., "Turning Eureka Steps into Calculations in Automatic Program", UK IT, (IEE Conf. Pub. 316), pp. 221-226, (1991).
Carlile, B.R., "Algorithms and Design: The CRAP APP Shared-Memory System", Compcon Spring '93, San Francisco, CA, pp. 312-320, (Feb. 22, 1993).
Chapman, B., et al., "Programming in Vienna Fortran", Dept. of Statistics and Computer Science, pp. 121-160.
Chien & J.H. Kim, A.A., "Planar-Adaptive Routing: Low-Cost Adaptive Networks for Multiprocessors", Pro. 19th International Symposium on Computer Architecture, pp. 268-277, (May, 1992).
Dally, W.J., et al., "Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels", I.E.E.E. Transactions on Parallel and Distributed Systems, vol. 4, No. 4, pp. 466-475, (Apr., 1993).
Dally, W., et al., "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", IEEE Transactions on Computer, C-36, pp. 547-553, (May, 1987).
Dally, W., "Performance Analysis of k-ary n-cube Interconnection Networks", IEEE Transactions on Computers, vol. 39, No. 6, pp. 775-785, (Jun., 1990).
Dally, W.J., "Virtual Channel Flow Control", Pro. 17th International Sympsoium on Computer Architecture, pp. 60-68, (May, 1990).
Debenedictis, E., et al., "Extending Unix for Scalable Computing", IEEE, pp. 43-53, (Nov., 1993).
Duato, J., "A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks", I.E.E.E. Transactions on Parallel and Distributed Systems, vol. 4, No. 12, pp. 1320-1331 (Dec., 1993).
Gallager, R., "Scale Factors for Distributed Routing Algorithms", NTC '77 Conference Record 2, pp. 2-1 through 2-5 (1978).
Glass, C.J., et al., "The Turn Model for Adaptive Routing", Pro. 19th International Symposium on Computer architecture, pp. 278-287, (May, 1992).
Gravano, L., et al., "Adaptive Deadlock-and Livelock-Free Routing with all Minimal Paths in Torus Networks", IEEE Transactions on Parallel and Distributed Systems, vol. 5, No. 12, pp. 1233-1251, (Dec., 1994).
Gupta, R., et al., "High speed Synchronization of Processors Using Fuzzy Barriers", International Journal of Parallel Programming 19 (1990) Feb., No. 1, New York, US pp. 53-73.
Gustavson, D.B., "The Scalable Coherent Interface and related Standards Projects", IEEE Micro, pp. 10-22, (Feb., 1992).
Ishihata, H., et al, "Architecture of Highly Parallel AP1000 Computer", Scripta Technica, Inc., Systems and Computers in Japan 24, No. 7, pp. 69-76, (1993).
Jesshope, C. r., M.Y., "High Performance Communications in Processor Networks", Communications in Processor Networks, Proc. 16th International Symposium on Computer Architecture pp. 150-157, (May, 1989).
Kirkpatrick, S, G.V., "Optimization by Stimulated Annealing", Science, pp. 671-680, vol. 220, No. 4598, (May, 1983).
Linder, D.H., et al., "An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes", I.E.E.E. Trans. on Computers, vol. 40, No. 1, pp. 2-12, (Jan., 1991).
Lui, Z., et al., "Grouping Virtual Channels for Deadlock-Free Adaptive Wormhole Routing", PARLE '93 Parallel Parallel Architectures and Languages Europe, 5th International PARLE Conference, Munich, Germany, pp. 255-265, (Jun. 14-17, 1993).
MacDonald, T., et al., "Addressing in Cray Research's MPP Fortran", Third Workshop on Compilers for Parallel Computers, pp. 161-172 (Jul. 7, 1992).
Nuth, P., et al., "The J-Machine Network", IEEE, pp. 420-423, (1992).
O'Keefe, M.T., et al., "Static Barrier MIMD: Architecture and Performance Analysis", Journal of Parallel and Distributed Computing No. 2., pp. 126-132, (Mar. 25, 1995).
Patterson, D.A., et al., "A Case for Redundant Arrays of Inexpensive Disks (RAID)", University of California at Berkeley, Report No. UCB/CSD 87/391, (Dec., 1987).
Scott, S., "The SCX Channel: A New, Supercomputer-Class System Interconnect", HOT Interconnects III, Abstract, pp. 1-11, (Aug

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Massively parallel processing system using two data paths: one c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Massively parallel processing system using two data paths: one c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Massively parallel processing system using two data paths: one c will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1457626

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.