Mass storage device architecture and operation

Details Mass storage device architecture and operation Mass storage device architecture and operation

2006-06-13

2006-06-13

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000

Reexamination Certificate

active

07062619

ABSTRACT:
A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

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