Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2003-04-29
2004-05-18
Huff, Mark F. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S322000, C427S250000, C427S561000, C427S576000, C216S083000, C216S018000, C134S902000
Reexamination Certificate
active
06737221
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a mass production technique of a semiconductor integrated circuit device, and more particularly, to a technique effectively applicable to a semiconductor production process, in which when a large number of wafers are continuously processed over a plurality of steps, the process is carried out in a mass production line wherein the lithographic step of wafers on which a film containing a transition metal such as ruthenium (Ru) is deposited and the lithographic step of wafers belonging to other steps are commonly used.
In the industrial fields other than that of the manufacture of a semiconductor, there is known a technique wherein a platinum group element is dissolved in a dissolution solution and isolated for the purpose of collecting the platinum group element from wastes or the like.
Japanese Laid-open Patent Publication No. Hei 7-157832 (Ito et al.) discloses a technique of recovering noble metals, such as gold, platinum group elements and the like, from used electronic parts, noble metal-containing, wasted catalysts, and a used jewelry by dissolution thereof in a dissolving solution. For the dissolution of noble metals, there is used a dissolving solution which is obtained by mixing an aqueous solution of an inter-halogen compound (e.g. ClF, BrF, BrCl, ICl, ICl
3
, IBr or the like) and an aqueous solution of a halogenated oxoacid (iodic acid, bromic acid, chloric acid or the like) at a ratio in the range of 1:9 to 9:1 The noble metal dissolved in the solution is first separated as a halogenated complex, to which a solution of a compound (e.g. sodium hydroxide, sodium borohydride, hydrazine or its salt, sulfurous acid or its salt, a bisulfite or the like) is then added, thereby collecting the metal.
Japanese Laid-open Patent Application No. Hei 7-224333 (Wada et al) discloses a technique of dissolving out, in the form of an aqueous solution, an alloy formed by nuclear fission and containing noble metals, such as ruthenium (Ru), rhodium (Rh), palladium (Pd) without undergoing such a pretreatment as by liquid metal extraction by immersing the alloy in a dissolving solution of hydroiodic acid (or hydrobromic acid), to which an iodine simple element is added. It is stated that the dissolving solution has a concentration of hydroiodic acid (or hydrobromic acid) ranging from 5 to 57 wt %, and a concentration of the added iodine simple element ranging from 0.01 to 0.5 moles per liter of the former aqueous solution.
SUMMARY OF THE INVENTION
In order to ensure an accumulated charge quantity of finely divided memory cells, a great capacitance DRAM (Dynamic Random Access Memory) of 1 Gbit or over has a capacitance insulating film of an information storage capacitor constituted of a high dielectric material such as an ABO
3
-type composite oxide having a specific inductive capacity of 100 or over, i.e. a perovskite composite oxide of BST (Ba, Sr) TiO
3
) For use as a capacitance insulating film material of the next generation, studies have been made on ferrodielectric materials having a perovskite crystal structure such as of PZT (PbZr
x
Ti
1-x
O
3
), PLT (PbLa
x
Ti
1-x
O
3
), PLZT, SBT, PbTiO
3
, SrTiO
3
and BaTiO
3
.
Where such a high/ferrodielectric material is used for the capacitance insulating film of a capacitor, it is necessary that conductive films for upper and lower electrodes sandwiching the capacitance insulating film therebetween should be each made mainly of a metal having high affinity for the high/ferrodielectric material, e.g. a platinum group metal (e.g. Ru (ruthenium), Rh (rhodium), Pd (palladium), Os (osmium), Ir (iridium) or Pt (platinum). Especially, ruthenium (Ru) is considered to be full of promise for use as an electrode material of a capacitor wherein the capacitance insulating film is constituted of such a high/ferrodielectric material because of its excellent etching controllability and film stability.
On the other hand, as a countermeasure for preventing an increase in wiring resistance caused by the scale down of a wiring width and the lowering of reliability in the field of high-speed logic LSI's, there has now been introduced copper wirings buried according to a so-called Damascene method. In the method, wiring grooves (and through-holes) are formed in an insulating film deposited on a substrate, and a copper (Cu) film having an electric resistance lower than an Al film is deposited on the insulating film including the inner surfaces of the wiring grooves (and the through-holes), followed by removal of an unnecessary copper film outside of the wiring grooves by a chemical mechanical polishing (CMP) method, the introduction of the buried copper wirings is now under study not only in the field of logic LSD, but also in the field of memories such as DRAM.
However, in order to introduce newcomer transition metals, such as the above-mentioned platinum group metals, perovskite-type high/ferrodielectrics and copper, which have never been in use in known wafer processes, and materials comprising the transition metals, into a semiconductor production process, it is essential to take a measure for preventing wafers from contamination with these transition metals. Especially, a transition metal such as copper has a great coefficient of diffusion in silicon (Si) and readily arrives at a substrate when undergoing an annealing step (thermal treatment step), with the great apprehension that it gives a serious adversely influence on device characteristics even at a very small concentration.
For instance, in the manufacturing process of general-purpose LSI's such as DRAM, a facility investment is suppressed to a minimum to reduce product costs, so that lithographic devices (such as a light exposure device and an EB exposure device), various types of inspection devices, and an annealing (thermal treating) device are commonly used in an initial element-forming step and a wiring step prior to the formation of a gate insulating film. These common devices are employed in the step of forming capacitors by use of such a newcomer material as set out hereinabove. More particularly, after transfer, from the common devices, of a wafer used for carrying out the capacitor-forming step, a fresh wafer used for carrying out the initial element-forming step or used for carrying out the wiring step is, in turn, transferred into the devices. In case where the buried copper wiring formed according to the Damascene method is provided as the wiring formed as an upper layer of the capacitor, a wafer having a copper film deposited on as an upper layer of the capacitor is transferred to the common devices for annealing (thermal treatment) after or prior to the transfer of another wafer to be subjected to other steps.
A film containing a platinum group metal, a perovskite-type high/ferrodielectric material or a transition metal such as copper, which has been deposited on the device side of a wafer according to a sputtering method or a CVD method, is also deposited on the outer marginal portions (edge portions) or the back side of the wafer. In this condition, when the wafer, from which the transition metal-containing film deposited on the outer edge portions or the back side of the wafer, is transferred to the common devices without removing the film to a satisfactory extent, a wafer stage, a wafer carrier, a conveyor and the like, which has come into contact with the outer edge portion or the back side of the wafer, are deposited on the surface thereof with the transition metal-containing film. This results in the contamination, with the transition metal, of a wafer which will be subsequently transferred to the common devices for performing lower layers steps (such as the step of forming an initial element and the wiring step prior to the formation of a gate insulating film).
Accordingly, in the mass production line for carrying out, by use of the common devices, the lithographic step for the wafer deposited thereon with a transition metal-containing film as stated above and the lithographic step for the wafers belonging to other
Futase Takuya
Kashi Mieko
Saeki Tomonori
Chacko-Davis Daborah
Huff Mark F.
Miles & Stockbridge P.C.
Renesas Technology Corp.
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