Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2008-01-02
2010-10-26
Rutz, Jared I (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S137000
Reexamination Certificate
active
07822920
ABSTRACT:
Disclosed herein is a mass prefetching method for disk arrays. In order to improve disk read performance for a non-sequential with having spatial locality as well as a sequential read, when a host requests a block to be read, all the blocks of the strip to which the block belongs are read. This is designated as strip prefetching (SP). Throttled Strip Prefetching (TSP), proposed in the present invention, investigates whether SP is beneficial by an online disk simulation, and does not perform SP if it is determined that SP is not beneficial. Since all prefetching operations of TSP are aligned in the strip of the disk array, the disk independence loss is resolved, and thus the performance of disk arrays is improved for concurrent sequential reads of multiple processes. TSP may however suffer from the loss of disk parallelism due to the disk independence of SP for a single sequential read. In order to solve this problem, this invention proposes Massive Stripe Prefetching (MSP). MSP includes an algorithm that detects a single sequential read at the block level. When a single sequential read is detected, prefetching is aligned in a stripe, and the prefetching size is set to a multiple of stripe size. Accordingly, the parallelism of disks is maximized.
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Baek Sung-Hoon
Park Kyu-Ho
H.C. Park & Associates PLC
Korea Advanced Institute of Science and Technology
Rutz Jared I
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