Maskless middle-of-line liner deposition

Details Maskless middle-of-line liner deposition Maskless middle-of-line liner deposition

2002-07-31

2004-11-23

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000, C257S334000, C257S510000, C257S513000

Reexamination Certificate

active

06822301

ABSTRACT:

BACKGROUND
This invention relates generally to semiconductor devices. In particular, the present invention relates to a process for manufacturing a semiconductor structure for a semiconductor memory device.
Semiconductor memory devices are currently in widespread use in electronic components that require retention of information. Semiconductor memory devices include random access memory (RAM), Dynamic Random Access Memory (DRAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and electrically erasable programmable read only memory (EEPROM) devices. Some DRAM devices include a core region and a periphery region. The core and periphery region include a plurality of transistors. Usually, the transistors are either vertical transistors or lateral transistors. As the size of the memory devices shrink, memory devices may include vertical transistors instead of lateral transistors in the core region so that the gate length may become independent of manufacturing limitations such as the core groundrule.
The core groundrule is the smallest distance or feature size that may be manufactured for a particular product. For example, for a DRAM memory device having a 0.17 micron groundrule, the gates in the core would be 0.17 microns wide and the distance in between two gates would also be 0.17 microns. As the technology moves to smaller core groundrules, e.g. 0.15 microns, 0.13 microns, or even 0.11 microns, the gate length would also typically shrink. However, shrinking the gate length leads to a larger sub-VT (voltage threshold) leakage. Sub-VT leakage is current leakage caused when electrical current flows underneath the gate from source to drain without opening the gate. Sub-VT leakage allows the capacitors to leak charge causing low retention time.
In the current process for manufacturing DRAM memory devices which use vertical transistors in the core, a contact etch is performed in the core to connect the semiconductor substrate to a series of contacts. The contact etch is performed through a middle-of-line (MOL) liner which typically consist of silicon nitride. The contact etch passes through a silicon oxide layer and a silicon nitride layer to make contact with the semiconductor substrate, and more particularly, an active crystalline silicon region within the semiconductor substrate. The semiconductor substrate is an ion implanted crystalline silicon. Unfortunately, the contact etch often etches a portion of the gate cap silicon nitride layer in addition to etching through the MOL liner, the silicon oxide layer and the silicon nitride layer. Etching a portion of the gate cap layer increases the risk of shorting between the bit-line and the word-line.
While the MOL liner is useful in the periphery region to prevent contamination of the transistors in the periphery region, the MOL liner is not required in the core region because there is already a prior layer of silicon nitride underneath the silicon oxide layer. Typically, a mask is used to remove the MOL liner from the core region and not the periphery region.
BRIEF SUMMARY
According to a first aspect of the present invention, a process for fabricating a semiconductor structure is provided. The semiconductor structure comprises a core region and a periphery region. The core region comprises a plurality of vertical transistors and the periphery region comprising at least one lateral transistor. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition, the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region. In one embodiment, the space between the transistors in the core region is less than the space between transistors in the periphery region, thus allowing more MOL liner to be deposited in the periphery region than in the core region. By having less MOL liner deposited in the core region than in the periphery region, the need for a mask to remove the MOL liner from the core region and not the periphery region is reduced or even eliminated.
In a second aspect of the present invention, a semiconductor structure is provided. The structure includes a semiconductor substrate having a core region and a periphery region. The structure also includes a plurality of transistors in the core region spaced a first distance apart, and plurality of transistors in the periphery region space a second distance apart, wherein the second distance is greater than the first distance. The structure also includes an oxide layer located in the core region overlying a nitride layer, and a middle-of-line liner overlying the semiconductor structure. The thickness of the nitride layer between the transistors in the core region is less than the thickness of the nitride layer between transistors in the periphery region.


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