Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2003-04-03
2004-08-17
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S794000, C438S799000
Reexamination Certificate
active
06777351
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture and, more particularly, to a method for providing a self-aligned mask over the surface of a semiconductor substrate assembly.
BACKGROUND OF THE INVENTION
During the formation of a semiconductor device such as memory devices, logic devices, microprocessors, etc., several photolithography steps are typically required. Each photolithography step includes the formation of a blanket photoresist (resist) layer, exposing portions of the resist layer to light using a mask or reticle, removing the exposed resist portions (or the unexposed resist portions if negative resist is used), etching the underlying layer using the resist as a pattern, then stripping the resist. To remove the resist, a high-temperature ash step is performed, then the wafer surface is exposed one or more times to an acid, typically a mixture of hydrogen peroxide (H
2
O
2
) and sulfuric acid (H
2
SO
4
), often referred to as a “piranha” process, to remove the resist ash which includes organic resins and metallic contaminants.
Photolithography adds significantly to the cost of semiconductor device production. Each photolithography step requires significant time, as the wafers must be moved from a station which deposits the resist, typically a spin-coat process, then to a stepper which exposes the resist using a mask or reticle. After the exposed or unexposed resist is removed, the wafer is moved to an etcher to etch the underlying layer, then to a furnace which ashes the resist, and finally to a piranha bath to remove the ashed resist. Photolithography also adds expense to the wafer as it requires materials including resist and acids and their eventual disposal, and also may decrease yields from misalignment of the mask.
During processing of a semiconductor device having a transistor array and a periphery, the array may require masking while the periphery remains exposed. Such a process may be used to form a silicide layer over the periphery while leaving the array free from the silicide. For example, in devices such as embedded dynamic random access memory arrays (DRAMs), it is desirable to form a silicide layer on the silicon wafer in the periphery which is not formed in the array. This is conventionally accomplished by forming a planarized sacrificial dielectric layer such as a phosphosilicate glass (PSG) layer, typically borophosphosilicate glass (BPSG), over the entire surface of the wafer, forming a patterned mask over the dielectric layer which exposes the periphery and covers other regions such as the array, etching the dielectric layer to expose the silicon wafer in the periphery and leaves dielectric over the array, forming a silicide region over the exposed silicon substrate, then removing the dielectric layer and any remaining resist.
As stated above, this process requires the formation of a dielectric layer and a resist layer, etching the dielectric layer to expose the silicon substrate, forming silicide, then removing the resist and dielectric layers. This process may cause scrap or rework by misalignment of the mask, results in additional materials and their disposal, and may possibly damage the silicon substrate during an undesirable over etch of the dielectric layer which may result in additional scrap or poorly-performing devices.
A method which decreases the number of photolithography steps during the manufacture of a semiconductor device would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which, among other advantages, reduces the number of photolithography steps required during the manufacture of certain designs of semiconductor devices. In accordance with one embodiment of the invention a layer is deposited under certain conditions set forth in the Detailed Description of the Preferred Embodiment. Under these conditions the doped oxide film will deposit thickly over areas having densely-packed topography, and will deposit more thinly over regions having widely-spaced topography. The thin deposited oxide layer over the widely-spaced topography may be removed using a blanket etch which leaves at least a portion of the thicker oxide layer over the densely-packed topography. Thus this use of the invention allows for a patterned layer over the densely-packed areas without using a photolithographic masking process. As the layer is self-aligned to the densely-packed regions, there is no chance of misalignment.
REFERENCES:
patent: 5438016 (1995-08-01), Figura et al.
patent: 5472904 (1995-12-01), Figura et al.
patent: 5753962 (1998-05-01), Jeng
patent: 6506647 (2003-01-01), Kuroda et al.
Cuneo Kamand
Martin Kevin D.
Micro)n Technology, Inc.
Sarkar Asok Kumar
LandOfFree
Masking without photolithography during the formation of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Masking without photolithography during the formation of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Masking without photolithography during the formation of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3338629