Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2002-12-30
2004-04-27
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S717000
Reexamination Certificate
active
06727126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to masking members for forming fine electrodes and manufacturing methods therefor, methods for forming electrodes, and field effect transistors, and more particularly, relates to a technique capable of forming finer electrodes usable, for example, as gate electrodes of field effect transistors.
The present invention is advantageously applied to the fields of field effect transistors having hetero structures, which are operated in microwave or milliwave bands, and integrated circuit devices formed by integration thereof with other components.
2. Description of the Related Art
In recent years, concomitant with the advancement of information technology (IT), higher capacity and higher speed communication systems have been increasingly requested, and improvements in transmission speed of communications have been further desired. In addition, in radio communications, radar and fixed communication systems used in milliwave bands have been increasingly demanded.
Under these industrial circumstances, for example, a compound semiconductor field effect transistor (FET) having a higher operation speed has been desired in recent years. In general, in order to improve the operation speed of an FET, in addition to increasing the electron speed in an active layer material, it can be highly effective to decrease the gate length of an FET.
In the past, gate lengths of approximately 500 nm and approximately 200 to 100 nm have frequently been used in a microwave band (up to several GHz) and a quasi-milliwave band (up to 30 GHz). However, in recent years, because of advancements in exposure methods and in fine processing techniques for resist material, by using an electron beam exposure method, for example, a gate length of 100 nm or less (a sub-hundred nanometer range of approximately 20 to 50 nm) has been realized. Actually, an FET using an extremely short gate has been experimentally formed, and high-speed properties and high-gain properties thereof have been confirmed in a milliwave band.
A gate electrode having the sub-hundred nanometer range described above is generally formed by a lithographic technique using an electron beam exposure method as described above, and in order to obtain a fine opening width using an opening pattern capable of forming a shape in conformity with a gate electrode to be formed, a resist material having a high electron beam sensitivity is used, and in order to form a gate electrode having a cross-sectional T-shape, a multilayer resist structure is used. The gate electrode is generally formed by deposition/lift-off, sputtering, or the like.
In the electron beam exposure method described above, since electron beams serve as the exposure source, and since the diameter of a convergent spot can be decreased by this method, it has been believed that the electron beam exposure method is most suitable for forming an extremely fine opening pattern having a length in the sub-hundred nanometer range.
However, according to this electron beam exposure method, since electron beams are converged and are then radiated, direct drawing must be performed at a position at which an opening portion is desired to be formed. That is, several thousand to several tens of thousands of areas at which gate electrodes of FETs are to be formed are present on one wafer, and all the areas mentioned above must be sequentially irradiated with electron beams to draw the patterns. In addition, if two or more gate electrodes are to be formed in one FET, it is easily estimated that an extremely long period of time is necessary to complete the exposure on one wafer.
On the other hand, according to a light exposure method, since exposure can be simultaneously performed in more than one chip area formed on a wafer, in contrast to the electron beam exposure method, exposure can be performed in an extremely short period of time.
However, in the light exposure method, since a light source having a wavelength of several hundred nanometers is used as an exposure source, the dimensions of an opening pattern to be formed are liable to be influenced by this wavelength, and hence it has been believed that the formation of a very fine pattern cannot be advantageously performed by a light exposure method.
Under the circumstances described above, attempts have been made to use a light exposure method for forming very fine patterns. According to a light exposure method using a conventional type of photomask (reticle), the limitation of fine pattern formation is approximately 300 nm; however, when an excimer laser (ArF or KrF) which is a short wavelength light source, a phase shift mask, a dummy gate process, or the like is used, the formation of a fine opening pattern having a length in the 100 to 200 nm range can be achieved even when a light exposure method is used.
In addition, according to patent publication 1, a method for decreasing an opening width of an opening pattern has been disclosed. The method comprises the steps of forming an opening pattern in a photoresist film formed on a semiconductor substrate by a photolithographic technique, and then performing heat treatment of the photoresist film at a temperature higher than a conventional post-baking temperature so that sidewall portions of the opening pattern formed in the photoresist film are distorted by being heated sufficiently to flow.
Furthermore, according to patent publication 2, a method has been disclosed in which a wall angle of a patterned resist film is controlled to be inclined by performing heat treatment of the patterned resist film. The purpose of this method is that when a gate electrode is formed by deposition, the opening formed in the resist film is not blocked by a gate metal material.
Patent publications 1 and 2 described above are Japanese Unexamined Patent Application Publication Nos. 6-104285 and 6-53251, respectively.
However, in the light exposure method, even when the technique described above capable of forming a finer pattern is used, opening dimensions having the sub-hundred nanometer range have still not been obtained as is the case in the past.
In particular, according to the technique disclosed in patent publication 1, since the side wall portions of the opening pattern are approximately uniformly distorted by heat, the thickness of an upstanding portion of the gate electrode is decreased, whereby disconnection of the gate electrode is liable to occur in the height direction, and in addition, the gate resistance may also be increased in some cases.
In addition, according to the technique disclosed in patent publication 2, since the wall angle of the resist film is controlled to be inclined, the opening width of the opening pattern formed in the resist film may be undesirably increased in some cases, and as a result, the object of forming finer electrodes cannot be obtained.
SUMMARY OF THE INVENTION
Accordingly, the present invention was made to solve the problems described above, and is able to provide a masking member (hereinafter referred to as “fine electrode-forming masking member”) for forming fine electrodes and a manufacturing method therefor, a method for forming electrodes, and a field effect transistor.
According to the present invention, although a light exposure method is used, a fine electrode-forming masking member having an opening width of 100 nm or less can be obtained, and when this fine electrode-forming masking member is used, a finer electrode, such as a gate electrode used for a field effect transistor or the like, can be formed without substantial increase in disconnection or resistance.
First, the present invention is used for forming fine electrodes on a substrate and relates to a method for manufacturing a fine electrode-forming masking member having opening patterns in conformity with the shape of the fine electrodes.
In order to solve the technical problems described above, the method of the present invention comprises a step of forming a first masking member having penetrating portions to be formed into the open
Inai Makoto
Sasaki Hidehiko
Tai Eiji
Murata Manufacturing Co. Ltd.
Ostrolenk Faber Gerb & Soffen, LLP
Pert Evan
Sarkar Asok Kumar
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