Masked arithmetic logic unit

Details Masked arithmetic logic unit Masked arithmetic logic unit

1982-07-06

1986-05-27

Thomas, James D.

Boots, shoes, and leggings

364768, G06F 738, G05F 750

Patent

active

045920052

ABSTRACT:
An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.

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Quanstrom, J. L., Programmable Logic Element Processor", IBM Technical Disclosure Bulletin, vol. 21, #10, Mar. 1979, pp. 3916-3918.

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