Mask write enablement for memory devices which permits selective

Details Mask write enablement for memory devices which permits selective Mask write enablement for memory devices which permits selective

1993-10-20

1999-05-25

Robertson, David L.

Static information storage and retrieval

Read/write circuit

Signals

365193, 365 51, G11C 700

Patent

active

059075120

ABSTRACT:
A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.

REFERENCES:
patent: 4636986 (1987-01-01), Pinkham
patent: 4653030 (1987-03-01), Tachibana et al.
patent: 4656605 (1987-04-01), Clayton
patent: 4683555 (1987-07-01), Pinkham
patent: 4758992 (1988-07-01), Taguchi
patent: 4888773 (1989-12-01), Arlington et al.
patent: 5012472 (1991-04-01), Arimoto et al.
patent: 5142637 (1992-08-01), Harlin et al.
patent: 5148523 (1992-09-01), Harlin et al.
patent: 5148524 (1992-09-01), Harlin et al.
patent: 5159676 (1992-10-01), Wicklund et al.
patent: 5175835 (1992-12-01), Beighe et al.
patent: 5329629 (1994-07-01), Horst et al.
Micron Technology, JEDEC Write-Per-Bit DRAM Module Proposal, Sep. 6, 1988, six pages.

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