Mask ROM with spare memory cells

Details Mask ROM with spare memory cells Mask ROM with spare memory cells

1991-08-22

1992-06-23

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365 94, 365104, 36523003, 371 101, G11C 700, G11C 2900, G11C 1700

Patent

active

051249480

ABSTRACT:
A main memory cell array is divided into a plurality of blocks, and a spare memory cell group is arranged apart from the main memory cell array. The spare memory cell group uses bit lines or word lines different from those of the main memory cell array and includes spare memory cells which are different in structure from the memory cells of the main memory cell array. The number of the memory cells of the spare memory cell group is the same as that of the main memory cells of one row or column in each block of the main memory cell array, and data can be programmed into the spare memory cells after the completion of the manufacturing process. The operation of programming data into the spare memory cells of the spare memory cell array is effected by use of a write-in address buffer and a write-in decoder. When a row or column including a defective memory cell is designated in the main memory cell array, the row or column of the spare memory cells in the spare memory cell group is activated.

REFERENCES:
patent: 4051460 (1977-09-01), Yamada et al.
patent: 4384345 (1983-05-01), Mikome
patent: 4385368 (1983-05-01), Principi et al.
patent: 4400798 (1983-08-01), Francis et al.
patent: 4422161 (1983-12-01), Kressel et al.
patent: 4493075 (1985-01-01), Anderson et al.
patent: 4556975 (1985-12-01), Smith et al.
patent: 4575743 (1986-03-01), Hashimoto
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4599709 (1986-07-01), Clemons
patent: 4601019 (1986-07-01), Shah et al.
patent: 4601031 (1986-07-01), Walker et al.
patent: 4610000 (1986-09-01), Lee
patent: 4648075 (1987-03-01), Segawa et al.
patent: 4672581 (1987-06-01), Waller
patent: 4675849 (1987-06-01), Kinoshita
patent: 4725980 (1988-02-01), Wakimoto et al.
patent: 4727516 (1988-02-01), Yoshida et al.
patent: 4807191 (1989-02-01), Flannagan
patent: 4811303 (1989-03-01), Hiroi
K. Takizawa et al., "Session XII: Gate and Programmable Logic Arrays, THPM 12.7: A 1Mb ROM with On-Chip ECC for Yield Enhancement," ISSCC 83, Feb. 24, 1983, pp. 158-159.

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