Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-11-05
2004-08-17
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06777762
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a memory structure and a method for fabricating the same. More particularly, the present invention relates to a structure of a mask programmable read-only memory (Mask ROM) and a method for fabricating the same.
2. Description of Related Art
A Mask ROM generally comprises a substrate, a plurality of buried bit lines in the substrate and a plurality of word lines crossing over the buried bit lines, wherein the substrate under the word lines and between the buried bit lines serves as the channel regions of the memory cells. A method for programming a Mask ROM comprises implanting ions into the channel regions of selected memory cells to raise their threshold voltages, which is called a coding implantation. The data (0/1) stored in a memory cell is dependent on the presence/absence of implanted dopants in the channel region.
In a conventional coding process of a Mask ROM, a photoresist layer is formed on the substrate and then patterned to form coding windows over the channel regions of selected memory cells. An ion implantation is then performed using the photoresist layer as a mask to dope the selected channel regions. However, since the coding windows do not distribute evenly and there must be some regions with dense coding window patterns (dense regions) and some with isolated coding window patterns (sparse regions) on the coding photo mask, the critical dimensions (CD) of the coding windows are not uniform. It is because the optical proximity effect (OPE) for the dense regions is stronger than that for the isolated regions, and the light intensity through the dense regions therefore is higher than that through the sparse regions. The CD deviations of coding windows cause misalignments of the coding implantation, which may results in severe coding errors to lower the reliability of the Mask ROM product.
To prevent CD deviations over the sparse regions and the dense regions, quite a few methods are proposed based on the use of phase shift masks (PSM) or on optical proximity correction (OPC) techniques. The OPC method forms assistant patterns on the photo mask to compensate the CD deviations caused by the optical proximity effect (OPE). However, the two methods both need to design special patterns on the photo masks, so the fabrication of the photo masks are time-consuming, expensive and difficult. Moreover, it is not easy to debug the patterns on such a photo mask after the photo mask is fabricated.
Moreover, a Mask ROM coding implantation is usually performed with boron ions in the prior art. However, the boron dopants implanted into the selected channel regions tend to diffuse laterally to the adjacent buried bit lines, while the boron ions may even be implanted into a portion of the adjacent buried bit lines because of the misalignments or CD deviations of the coding mask. Therefore, the dopant concentrations of the buried bit lines are lowered to cause higher resistance and smaller electric current.
SUMMARY OF INVENTION
Accordingly, this invention provides a Mask ROM and the fabrication thereof to prevent diffusion of the implanted coding dopants into the buried bit lines and thereby avoid the current in the buried bit lines from decreasing.
This invention also provides a Mask ROM and the fabrication thereof to improve the coding accuracy without using phase shift masks (PSM) or optical proximity correction (OPC), so as to reduce the cost for fabricating the photo mask.
A Mask ROM of this invention comprises a substrate, a gate dielectric layer, a plurality of gates, a plurality of buried bit lines, an insulator, a plurality of word lines and a coding layer. The gates are disposed over the substrate, and the gate dielectric layer is disposed between the substrate and the gates. The buried bit lines are located in the substrate between the gates, and the insulator is disposed on the buried bit lines and between the gates. Each word line is disposed over a row of gates and the insulator perpendicular to the buried bit lines. The coding layer is disposed between the word lines and the gates to constitute a plurality of memory cells, and comprises a material such as semiconductor. Some memory cells are implanted with coding ions and are in a logic state of 1 (or 0), and the other memory cells are not implanted with coding ions and are in a logic state of 0 (or 1).
A method for fabricating a Mask ROM of this invention is described as follows. A gate dielectric layer is formed on a substrate, and then a strip conductive structure is formed on the gate dielectric layer. An ion implantation is performed using the strip conductive structure as a mask to form a buried bit line in the substrate beside the strip conductive structure. Thereafter, the strip conductive structure is patterned perpendicular to the buried bit line to form a plurality of gates. An insulator is formed between the gates by, for example, forming an insulating layer on the substrate covering the gates and then performing a CMP process or an etching-back process to remove a portion of the insulating layer until the gates are exposed. Then, a material layer and a conductive layer are sequentially formed over the gates and the insulator, wherein the material layer comprises a material such as semiconductor. The conductive layer and the material layer are sequentially patterned to form a word line over the gates perpendicular to the buried bit line and a coding layer under the word line, wherein the coding layer constitutes a plurality of memory cells. A coding mask is formed on the substrate. An implantation is then performed using the coding mask as a mask to dope selected memory cells, wherein the selected memory cells are in a logic state of 1 (or 0), and the other memory cells are in a logic state of 0 (or 1).
Since the coding ions are implanted into the coding layer between the gates and the word line, the dopants do not diffuse to the buried bit lines to decrease the electric current in the buried bit lines. Meanwhile, the buried bit lines are not affected even with misalignments or CD deviations of the coding mask, so phase shift masks (PSM) or optical proximity correction (OPC) procedures are not required.
Accordingly, this invention is capable of increasing the margin of the Mask ROM coding process.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5688661 (1997-11-01), Choi
patent: 5990527 (1999-11-01), Wen
patent: 6251731 (2001-06-01), Wu
J.C. Patents
Lee Eddie
Macronix International Co. Ltd.
Owens Douglas W.
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