Mask ROM fabrication method

Details Mask ROM fabrication method Mask ROM fabrication method

1999-08-12

2001-09-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S587000

Reexamination Certificate

active

06291308

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a mask ROM capable of effectively reducing the distance between buried impurity diffusion regions.
2. Description of the Related Art
As the level of integration of semiconductor devices increases, the scaling-down of a pattern pitch, that is, decreasing the line width of a circuit, becomes a center of interest. Such a decrease in line width of a circuit is achieved by developing photolithography technology. The line width of the circuit is determined by various factors, e.g., resolution of a photoresist used for manufacturing a pattern or wavelength of light (the shorter wavelength is favorable for a small pattern). Decreasing the line width of circuits, that is, decreasing the pitch, is very important to more highly integrated semiconductor devices, and is a trend which is likely to become more emphasized in the future.
As mentioned above, a semiconductor device can be reduced by decreasing a wavelength of light which is one of the important factors that determine the resolution of a photoresist used for a photolithography process. The light used for photolithography has been changed from g-line having a wavelength of 426 nm, used initially, to I-line having a wavelength of 265 nm used at the present. Also, a KrF excimer laser of 248 nm will be used in the future as a light source for photolithography. Also, the resolution increases such that an aperture of an exposure device used during the photolithography is enlarged and the wavelength of light decreases.
However, if the size of a semiconductor device is reduced by the above-mentioned method, investment costs for equipment capable of producing a new generation semiconductor device increase logarithmically. Such a high-cost investment according to the high integration of a semiconductor device in addition to the shortened life cycle of a product becomes a burden to a manufacturer. Thus, much attention has been devoted to a method capable of increasing the degree of integration of a device as well as of minimizing investment costs.
FIG. 1
is a plan view of a cell array region of an NOR type mask ROM, and
FIGS. 2A through 2D
are sectional views cut along lines a-a′, b-b′, c-c′ and d-d′ of FIG.
1
.
In
FIG. 1
, reference character P
1
represents a buried impurity diffusion region, reference character P
2
represents a word line (that is, gate electrode), reference character P
3
represents a metal interconnection, and reference character P
4
represents a mask pattern for controlling a threshold voltage of a channel region (that is, for programming).
The buried impurity diffusion regions P
1
are separated by a predetermined distance, parallel to each other. The word lines P
2
are perpendicular with respect to the buried impurity diffusion regions P
1
, and separated by a predetermined distance like the buried impurity diffusion regions P
1
. The metal interconnections P
3
are arranged parallel to the buried impurity diffusion regions P
1
. The mask patterns P
4
for controlling a threshold voltage of a channel region are arranged in a channel region of a designated cell requiring programming. The buried impurity diffusion regions serve as a source/drain of a cell transistor and a bit line.
Referring to
FIG. 1
, each cell is formed along the word line, and a portion where the buried impurity diffusion region overlaps with the word line becomes a source/drain, and a lower portion of the word line which does not overlap the buried impurity diffusion region becomes a channel region.
In
FIGS. 2A through 2D
, reference numeral
10
represents a semiconductor substrate, reference numeral
12
represents a buried impurity diffusion region, reference numeral
14
represents a gate oxide layer, reference numeral
16
represents a word line (i.e., gate electrode), reference numeral
18
represents an insulation layer for preventing the gate electrode, reference numeral
20
represents an interlayer dielectric (ILD) film, reference numeral
22
represents a metal interconnection, and reference numeral
24
represents an insulation layer for preventing the metal connection. in
FIG. 2A
, a region marked with “+” represents a designated channel region which requires programming and impurities are implanted into this region to control a threshold voltage.
The buried impurity diffusion region
12
overlapped with the word line
16
becomes a source/drain of each cell, and a lower region of the word line
16
located between the buried impurity diffusion regions
12
becomes a channel region.
The operation of a cell of a NOR type mask ROM will now be described. A voltage of 0~2V is applied to a bit line connected to a specified cell from which a programed data is read, and neighboring bit lines are grounded, and a high voltage is applied to a word line of the specified cell. Here, if the threshold voltage of a channel region of the specified cell is programed to be higher than the highest voltage, the specified cell is turned off when it is read as being in an “off” state, so that discharging of the bit line is prevented. If the threshold voltage of the channel region of the specified cell is programmed to be lower than the high voltage, the specified cell is turned on when it is read as being in an an “on” state. Each bit line is connected to a source of a select transistor (not shown) formed at the edge of each buried impurity diffusion region, and voltage is supplied to the buried impurity diffusion region by the operation of the select transistor.
In general, a cell is programed into two states according to whether the threshold voltage of the channel region of each cell is higher or lower than the voltage supplied to the gate electrode of each cell. Here, the threshold voltage of the channel region of each cell is controlled using the mask pattern P
4
shown in FIG.
1
.
Also, in order to increase the degree of integration of the mentioned mask ROM, it is important to reduce the area occupied by the cells therein. In the most favorable method for integration, referring to
FIG. 1
, the pitch of the buried impurity diffusion region P
1
(see FIG.
1
), which refers to the distance between a buried impurity diffusion region and another buried impurity diffusion region, and the pitch of the word line P
2
(see FIG.
1
), which refers to the distance between a word line and another word line, are reduced in order to decrease the unit area occupied by each cell.
However, there are the following considerations.
First, in the case of reducing the pitch of the buried impurity diffusion region, a decrease in length of the channel region should be considered. That is, it should be assumed that punch-through margin of a cell transistor is secured even though the pitch of the buried impurity diffusion region is reduced by photolithography. In the case of reducing the pitch of the word line, a decrease in width of the channel region should be considered. That is, even though the pitch of the word line is reduced by photolithography, the decrease in drain current according to a decrease in the width of the channel region should be considered. A decrease in drain current requires another consideration in designing, such as sensing the margin of a bit line. In consideration of the electrical characteristics of a mask ROM, if the punch-through margin of the cell transistor is secured, it is preferable to reduce the pitch of the buried impurity diffusion region, thereby providing many advantages in designing.
FIGS. 3A through 3C
are sectional views illustrating a conventional method for forming a buried impurity diffusion region.
After stacking a pad oxide layer
28
and a silicon nitride layer
30
on a semiconductor substrate
26
in sequence, a portion of the silicon nitride layer
30
, stacked in an isolation region of a peripheral circuit region (n-channel and p-channel regions), is removed by photolithography using a first pho

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