Mask ROM device having double polycrystalline silicone and proce

Details Mask ROM device having double polycrystalline silicone and proce Mask ROM device having double polycrystalline silicone and proce

1990-08-31

1992-09-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437193, 437195, 357 41, 357235, H01L 2170, H01L 2700

Patent

active

051496674

ABSTRACT:
A mask ROM device having a NAND type high integration double polycrystalline silicon and a process for producing the same. The invention includes a first conductive type semiconductor substrate, a field oxide film, a channel stopper, a second conductive type diffusion region, third and fourth conductive type channels, a gate oxide film, a number of first polycrystalline silicon gates, a number of second polycrystalline silicon gates, insulating film, and a metal film the metal film is manufactured by forming an ion plantation region, a third conductive type channel, and forming sequentially a first gate oxide film, a first gate electrode substance oxide film, a nitride film and LTO film, etching all of them whereby forming a first gate electrode and exposing the substrate, forming a spacer, a second gate electrode, an opening, and programming into a fourth conductive type channel, and forming a diffusion region or source and rain, and then forming an insulating film, connecting opening, and a metal film. According to the invention, the area of the chip can be greatly reduced, reliability can be improved because it is programmable only to selected memory cells. Resistance of the word line is decreased, and active resistance is decreased.

REFERENCES:
patent: 4328563 (1982-05-01), Schroeder
patent: 4665295 (1987-05-01), McDavid
patent: 4696092 (1987-09-01), Doering et al.
patent: 4818716 (1989-04-01), Okuyama et al.
patent: 4851365 (1989-07-01), Jeuch

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