Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-26
2003-09-02
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S922000
Reexamination Certificate
active
06614080
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to integrated circuits, and in particular, to a read only memory (ROM) device.
BACKGROUND OF THE INVENTION
Configurations of functional integrated circuits, standing programs in digital devices such as microcomputer and/or microprocessor systems, non-modifiable codes and other data permanently data stored in “smart cards” and similar integrated devices are commonly stored in read only memory (ROM) devices. ROM devices are formed by a manufacturer of semiconductor devices according to specification and coding of the customer.
Data are permanently stored in ROM devices at a certain step of their fabrication process. As in any other static memory device composed by a matrix of cells ordered in rows and columns and individually addressable through mutually orthogonal lines, called wordlines and bitlines, the logic value of each single bit is set by making conductive or non-conductive the corresponding cell. According to a common convention, a conductive cell corresponds to the logic value 0 while a non-conductive cell corresponds to the logic value 1.
Such ROM devices are customized a customization at a certain point of the fabrication process. For economic reasons it would be preferable to carry out the permanent storage of data in the cells of the memory matrix as late as possible in the fabrication process. This would be done in order to follow the steps of a standard process as far as possible before such a necessary customizing step, thus allowing important scale production savings.
Generally each single cell is formed by a field effect transistor, typically a MOS transistor, whose source is commonly connected to a common node at a reference voltage, typically a ground voltage. Transistors (cells) disposed along a same row of the matrix or of a block or sector in which the whole matrix may be subdivided, share a control electrode or gate that functions also as an address wordline.
Traditionally the programming of the ROM matrix is carried out by using a dedicated mask to establish a connection for the drain of each single cell to the respective address bitline. The unconnected cells will provide the logic data 1 while the connected cells will provide the logic data 0, according to the commonly adopted convention.
For the above mentioned economic reasons of mass production, alternative programming systems have been developed that are no longer based on the realization of a physical electrical connection of the drain region of the single cell. Alternative programming techniques are based on carrying out dopant implants in areas corresponding to the drain region of selected cells through dedicated masks. This is done in order to raise the turn-on threshold of the MOS transistor to a sufficiently high level for all the cells to be programmed in a non-conducting state, i.e., a logic 1. Typically, these implants are carried out at relatively high energies through pre-formed insulating and interconnecting layers. Though these alternative techniques satisfy the need of carrying out the customization as late as possible in the fabrication process of the device, they tend to become unsuitable with the scaling down of integrated circuits.
In new and future ULSI devices, where minimum dimensions (linewidth) may be on the order of decimal fractions of &mgr;m, these programming techniques by masked high energy implants loose reliability, and in such demanding conditions it has been found necessary to use a classic programming technique. This programming technique is performed by establishing an electrical connection to the drain of the cells to be programmed in a conductive state. This is done by using modern techniques to form contacts based on the filling of contact holes of extremely small dimensions with a refractory metal that can be deposited from a vapor phase, such as a chemical vapor deposition (CVD). Plugs formed by tungsten or of any other equivalent metal are then connected by intercepting conductive lines defined in a first level metallization layer (metal
1
), such as aluminum, for example.
U.S. Pat. No. 5,925,917 discloses a ROM device and a relative fabrication method. The source and drain contacts on all the cells of the memory array are formed according to normal techniques for defining open contact holes through an insulating dielectric layer, and for successively filling them by depositing and attacking a filler metal defining contacts. A second dielectric layer is deposited through which, using a dedicated programming mask for “interconnection contacts”, are opened to establish an electrical continuity with the underlying filler metal plugs of the contacts relative to the cells to be programmed in a conductive state.
Special circuit configurations, programs and codes, personal codes and similar data commonly intended to be stored in such ROM devices are proprietary information of the customer and/or of the person to whom data and codes permanently stored in the ROM memory device pertain. It is evident that such information is confidential and must be made undecipherable as much as possible. Modern optical inspection techniques, i.e., with a microscope, commonly used in reverse engineering operations are able to detect the programming features of a ROM array and thus to access codes and data that are permanently stored in it.
Indeed, the interconnection contacts formed through the second dielectric layer according to the method described in the above referenced patent can be easily recognized even if intercepted, i.e., partly covered, by a first level metal line (metal
1
) patterned on the surface of the second dielectric layer. In practice, the point along the metal line at which there is an interconnection contact underneath can be easily discriminated from a point at which the expected interconnection contact is in fact absent. In this way the cells programmed as a 0 can be easily discriminated from cells programmed as a 1 thus allowing the deciphering of data stored in the ROM memory.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a read only memory structure formed according the most advanced fabrication techniques and is programmable by using a dedicated mask, with the stored data being substantially undecipherable by a reverse engineering technique including optical inspection with a microscope.
This and other objects, advantages and features are provided by forming interconnection contacts and false interconnection contacts through a second insulating dielectric layer formed on a first insulating dielectric layer through which source contacts and drain contacts of the memory cells to be programmed in a conductive state have been previously formed. This completes the electrical connection of the drain contacts of the cells programmed in a conductive state to the respective bitline defined in metal
1
, while producing at the same time false interconnection contacts to the respective bitlines of memory cells programmed in a non-conductive state and thus not having an underlying drain contact.
In this way even carrying out reverse engineering operations on the device, the optical inspection will not clearly detect the presence of true interconnection contacts and false interconnection contacts so that they will be practically indistinguishable from one another. The deciphering of data permanently stored in the read only memory array could take place only by carrying out and analyzing microsections of such a large number of devices, which would be economically prohibitive.
REFERENCES:
patent: 5383149 (1995-01-01), Hong
patent: 5600171 (1997-02-01), Makihara et al.
patent: 5925917 (1999-07-01), Maari
patent: 0186855 (1986-07-01), None
patent: 0666599 (1995-08-01), None
Patent Abstracts of Japan, vol. 1998, No. 14, Dec. 31, 1998 and JP 10256398A (Nippon Steel Corp.), Sep. 25, 1998.
Patelmo Matteo
Vajana Bruno
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Flynn Nathan J.
Jorgenson Lisa K.
Quinto Kevin
STMicroelectronics S.r.l.
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