Mask-programmable ROM cell

Details Mask-programmable ROM cell Mask-programmable ROM cell

2001-06-27

2003-09-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C365S185180, C365S185140

Reexamination Certificate

active

06629309

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication, and more particularly to methods, structures and masks associated with programming an identification code into an integrated circuit.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuit manufacturers often find it useful to include an identification code, or “device ID,” within a manufactured integrated circuit. The code is generally contained within a set of memory cells, such as a register, which is externally readable, often during test of the integrated circuit (IC). The circuit identification code may provide information on, for example, the manufacturer, the particular circuit design, and/or the process used to fabricate the circuit. Identifying an integrated circuit using a device ID may allow close synchronization of the integrated circuit device design with back-end processing steps. Such back-end processing steps may include, for example, testing individual devices or attachment of individual devices to printed circuit boards. Identification codes may be particularly useful for manufacturers producing many diverse ICs, such as manufacturers of custom-designed application-specific integrated circuits (ASICs). Identification may also provide an opportunity for the end users of a product to resolve certain inventory problems in an unambiguous way.
In some cases, an identification code is externally programmed into a programmable, read-only register dedicated for that purpose. It is generally desired that the register be read-only in order to minimize the possibility that its contents will be altered during subsequent processing. The programming may take place during, for example, an initial wafer sort test. Although such external programming may allow additional information to be represented by an identification code, such as die-specific test performance information, there are disadvantages to this approach. In particular, external programming may be error-prone in that the possibility exists for the wrong code to be inadvertently programmed into a particular circuit's identification register, which then renders that particular device useless to the extent that the device must be properly identified using the code. Also, non-volatile registers require the availability of special processing steps, which in themselves represent an added cost element.
An alternative approach is to design the metallization of the integrated circuit to directly wire the memory cells to on-chip programming voltages. The programming voltages are typically power supply voltages for the chip, so that the identification code is programmed into the identification register upon any power-up of the device (during testing, for example). Such internal programming of the circuit identification code may involve multiple mask levels of the integrated circuit, which are discussed briefly below.
Integrated circuit fabrication typically requires the use of multiple photolithography masks. Each mask is used to transfer a pattern to an upper layer of the semiconductor topography from which the circuit is formed, where the semiconductor topography includes a semiconductor wafer and the various layers and structures formed upon and within the wafer during the IC fabrication process. Multiple photolithographic masking steps are performed at various stages of the process, with patterning of one layer often followed by formation of and patterning of an additional layer. Generally, photolithography begins with formation of a layer of a photosensitive material called photoresist over the semiconductor topography. The photoresist is exposed to radiation through an appropriately patterned mask, so that properties of the photoresist are altered by the radiation in a pattern corresponding to the mask pattern. Depending on the particular type of the photoresist, either exposed or unexposed portions of the photoresist are then preferentially removed. The resulting photoresist pattern may be transferred to the underlying semiconductor topography, by processes such as etching or implantation of dopant impurities, as appropriate for the particular layer of the IC being formed.
During the product life cycle of an IC, various revisions may be made to its design and/or fabrication process. In fact, such revisions are often made during initial testing of a circuit design before the first devices are sold. Such revisions often involve changes to the mask used for patterning of a particular layer within the circuit. It is desirable in such cases to change the circuit identification code of a circuit undergoing a revision. Different codes can be used to distinguish one revision of the device from another, for example, or to later identify a particular mask or sequence of masks used to form a device.
In the case described above of a circuit identification register having its memory cells internally wired to programming voltages, however, changing the circuit identification code may require modification of multiple masks used to fabricate the integrated circuit. This can result in excessive time and expense, particularly in a case for which the revision of the circuit design requires changing of only one or two masks. It would therefore be desirable to develop a method of altering the circuit identification code of an IC when a mask pattern change is implemented. The code alteration should require changes to a minimal number of masks, and should not require excessive area on the circuit to implement.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a structure described herein for programming a memory cell on an integrated circuit. The structure provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In a preferred embodiment, there are two programming voltages used: the upper polarity of the circuit's power supply (typically called “V
DD
” or “V
CC
”), and the lower polarity of the power supply (typically called “V
SS
,” and usually at ground potential). Application of V
DD
to the input of the memory cell would typically program a logical “1” into the cell, while application of V
SS
would program a “0.” In such an embodiment, both V
DD
and V
SS
are available at multiple mask levels, so that modification of a single mask can be used to change the value programmed into the memory cell. Preferably, all of the programming voltages are accessible at each mask level within the circuit involving either patterning of a conductor or formation of contacts or vias between conductor layers.
In an embodiment, the structure includes a conductive signal path extending through multiple horizontally conductive layers of the integrated circuit from a programming voltage pad (or node) to an input of the memory cell. The multiple horizontally conductive layers may be stacked above one another, such that the conductive signal path is in a generally vertical direction. A “horizontally conductive layer” as used herein is a layer having conductive structures arranged in a primarily horizontal direction (parallel to a polished surface of the semiconductor substrate on which the circuit is formed). A horizontally conductive layer may therefore be an interconnect layer, including patterned conductive interconnect lines. Such interconnect lines may be formed from metal, or other conductive materials such as polysilicon, which might be used in a local interconnect level. Patterned doped regions within the semiconductor substrate could also form a horizontally conductive layer. The horizontally conductive layers typically have via or contact layers interposed between them, where the via/contact layer is a dielectric layer having conductive vias or contacts formed therethrough. “Via” is typically used to describe vertical connections between metal lines, while “contact” may be used to des

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