Mask programmable read only memory

Details Mask programmable read only memory Mask programmable read only memory

2003-09-23

2004-10-19

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S230070

Reexamination Certificate

active

06807112

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a semiconductor integrated circuit device. More particularly, the invention relates to a memory cell and circuit technology that achieve speed enhancement in view of process miniaturization of a mask ROM (mask programmable ROM), a type of ROM that can be programmed using a mask.
2. Description of the Prior Art
A semiconductor memory device of the prior art is disclosed, for example, in Japanese Unexamined Patent Publication No. H06-176592. In the cited patent publication, the configuration of a contact mask programmable ROM is described in paragraphs 0002 to 0006 on page 2 with reference to FIG.
2
.
FIG. 7
is a circuit diagram showing the configuration of the such a contact mask programmable ROM. The contact mask programmable ROM is a ROM that stores data “1” or “0” depending on whether the drain of a memory cell transistor is connected or not connected to its associated bit line. This mask ROM can be programmed using a mask.
The semiconductor memory device of the prior art comprises, as shown in
FIG. 7
, a column decoder
2
, a buffer
3
, a precharging transistor
4
, a memory cell array
7
, and an off-leakage charge replenishing transistor
8
.
The column decoder
2
comprises N-type MOS transistors QCj (j=1 to n). The drains of the N-type MOS transistors QCj are connected in common, while their sources are connected to respective bit lines BLj (j=1 to n), and their gates to respective column select signal lines CLj (j=1 to n).
The input end of the buffer
3
is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder
2
, and its output end is connected to a data output terminal SOUT.
The precharging transistor
4
is constructed from a P-type MOS transistor. The gate of the precharging transistor
4
is connected to a precharge control signal line PCLK
1
, the source is connected to a power supply terminal having a power supply potential, and the drain is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder
2
.
The memory cell array
7
is a matrix array of memory cells M(i, j) (i=1 to m, j=1 to n) each constructed from an N-type MOS transistor. The gates of the memory cells M(i, j) having the same value of i, that is, arranged in the same row, are connected in common to the same word line WLi (i=1 to m). The sources of these memory cells M(i, j) are connected to a ground potential line GL. The drain of each memory cell is connected to its associated bit line BLj (j=1 to n) when the data stored therein is “1”, but is held in a floating state when the stored data is “0”.
The off-leakage charge replenishing transistor
8
is constructed from a P-type MOS transistor. The gate of the off-leakage charge replenishing transistor
8
is connected to the output end of the buffer
3
, the source is connected to the power supply terminal, and the drain is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder
2
. The ON current of the off-leakage charge replenishing transistor
8
is chosen to be smaller than the ON current of the memory cells M(i, j) (i=1 to m, i=1 to n).
The operation for reading data from the memory cell M(
1
,
1
) in the thus constructed semiconductor memory device will be described with reference to the timing diagram of FIG.
8
.
Of the column select signal lines CLj (j=1 to n), the column select signal line CL
1
is driven to the “H” level, while holding the other column select signal lines CL
2
to CLn at the “L” level; as a result, of the N-type MOS transistors QCj (j=1 to n) forming the column decoder
2
, the N-type MOS transistor QC
1
is ON, and the other N-type MOS transistors QC
2
to QCn are OFF.
Next, the precharge control signal line PCLK
1
is driven to the “L” level for a period Tp, thus causing the precharging transistor
4
to turn on for the duration of the prescribed period Tp. As a result, the bit line BL
1
is charged to the “H” level.
After the bit line BL
1
has been charged to the “H” level, of the word lines WLi (i=1 to m) the word line WL
1
is raised from the “L” level to the “H” level, while holding the other word lines WL
2
to WLm at the “L” level.
Here, when the drain of the memory cell M(
1
,
1
) is connected to the bit line BL
1
, the charge stored on the bit line BL
1
and the charge supplied from the off-leakage charge replenishing transistor
8
are discharged through the memory cell M(
1
,
1
), and the bit line BL
1
goes to the “L” level, so that the input to the buffer
3
is also at the “L” level. As a result, after a delay of time Tac
3
, “H” is read out at the data output terminal SOUT, and the off-leakage charge replenishing transistor
8
turns off (indicated by dashed lines in FIG.
8
).
On the other hand, when the drain of the memory cell M(
1
,
1
) is not connected to the bit line BL
1
, the charge stored on the bit line BL
1
is not discharged through the memory cell M(
1
,
1
), the bit line BL
1
is held at the “H” level, so that the input to the buffer
3
is also at the “H” level. As a result, “L” is read out at the data output terminal SOUT, and the off-leakage charge replenishing transistor
8
turns on. The charge being discharged due to the off-leakage currents of the other memory cells (i,
1
) (i=2 to m) whose drains are connected to the bit line BL
1
is replenished by the off-leakage charge replenishing transistor
8
turning on. Accordingly, the bit line BL
1
is held at “H”, and the data output terminal SOUT can thus continue to read out “L” (indicated by solid lines in FIG.
8
).
In the prior art, the semiconductor memory device has the following problem. In the semiconductor memory device, the drains of a plurality of memory cells whose sources are grounded are connected to the same bit line, depending on the values of their stored data. As a result, a steady state current occurs on the bit line due to the off leakages of the plurality of memory cells.
Therefore, when reading data from a memory cell whose drain is not connected to the bit line, the charge being discharged as a result of the steady state current occurring due to the off leakages of the memory cells must be replenished in order to keep the bit line at the “H” level; the off-leakage charge replenishing transistor
8
is provided to supply the necessary charge to the bit line.
In recent years, with the rapid advance of miniaturization, the off-leakage current of a transistor forming a memory cell has been increasing at an extraordinarily rapid pace; as a result, the ON current of the off-leakage charge replenishing transistor for supplying charge to the bit line to make up for the charge being discharged as a result of the steady state current occurring due to the off leakages must also be increased.
For a memory cell whose drain is connected to the bit line, this in turn means that, when reading the data stored in the cell by discharging the bit line and thereby driving the bit line to the “L” level, it takes a long time for the charge supplied from the off-leakage charge replenishing transistor to be discharged through the ON current of the memory cell. The resulting problem is that the data cannot be read out at high speed.
SUMMARY OF THE INVENTION
The present invention has been devised to solve the prior art problem of the semiconductor memory device described above, and an object of the invention is to provide a semiconductor memory device that can hold the bit line at the “H” level without needing the off-leakage charge replenishing transistor, and can accomplish readout at high speed.
A semiconductor memory device according to the present invention comprises: a plurality of memory cell transistors arranged in a matrix form; a plurality of bit lines and a plurality of word lines to which drains and gates of the memory cell transistors are respec

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