Mask-programmable logic devices with programmable gate array...

Details Mask-programmable logic devices with programmable gate array... Mask-programmable logic devices with programmable gate array...

2002-03-29

2004-05-25

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06742172

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to mask programmable logic devices, and more particularly, to mask programmable logic devices that include gate array sites.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration information in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic elements in the device, and the interconnect for routing of signals between the logic elements, were programmable. Another variant is a mask-programmable logic device. With mask-programmable logic devices, instead of selling all users the same device, the manufacturer produces a partial device with a standardized arrangement of logic resources whose functions are not programmable by the user, and which lacks any routing or interconnect resources.
The user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device. The manufacturer uses that information to add metallization layers to the partial device described above. Those additional layers program the logic elements by making certain connections within those elements, and also add interconnect routing between the logic elements. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration also is accomplished using the additional metallization layers.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, a conventional programmable logic device invariably includes resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resources, and the switching resources that allow signals from any logic element to reach any desired routing and interconnect resource, conventional programmable logic devices grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching elements as they travel from one routing and interconnect resource to another also slows down signals.
The advent of mask-programmable logic devices has allowed users to prove a design in a conventional programmable logic device, but to commit the production version to a mask-programmable logic device which, for the same functionality, can be significantly smaller and use significantly less power, because the only interconnect and routing resources are those actually needed for the particular design. In addition, there are no general purpose switching elements consuming space or power, or slowing down signals.
However, mask-programmable logic devices do not contain predefined routing resources. Therefore, the task of creating the customized interconnect for each design falls to the manufacturer in migrating the user's programmable device design to a mask-programmable device. This task is time consuming, and significantly slows down the process of migrating the design. The migration process is further complicated by the fact that certain implementation-related problems such as timing and testability violations and signal attenuation are not apparent until after an initial mask-programable device is fabricated and tested. Fixing such problems often requires redesign of the custom interconnect and/or reallocation of logic resources on the base device. This solution, however, often requires the fabrication of multiple devices to prove a given design and is therefore costly and time consuming.
Accordingly, it would be desirable to provide a way to quickly and effectively solve implementation problems by providing resources that allow some modifications to be made to the original mask design that do not involve the costly or time consuming tasks of reallocating logic resources or redesigning the customized interconnect.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a way to quickly and effectively solve implementation problems by providing resources that allow modifications to be made to the original mask design that do not involve the costly or time consuming tasks of reallocating logic resources or redesigning the customized interconnect.
This and other objects of the invention are accomplished in accordance with the principles of the present invention by providing configurable gate array sites disposed on an integrated circuit for correcting implementation problems.
In one embodiment of the present invention, configurable gate array sites are disposed in various locations throughout the device to correct buffering and timing violations that may result from the streamlining of a device's interconnection and logic resources. Such gate array sites may be fabricated on a device substrate and each site may include a plurality of circuit elements (e.g., transistors) for forming fundamental logic gates. To correct a particular problem, a gate array cell that provides the desired function may be formed on a gate array site proximal to the point in the device where the violation manifests itself. This cell may be formed by interconnecting certain circuit elements found in the gate array site to obtain the desired logic function.
In another aspect of the invention, each gate array site may have some or all of its interconnections and contact points coupled to the substrate in order to reduce the cost of adding an additional contact layer mask.


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