Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-05-28
2001-04-03
Teska, Kevin J. (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06212671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as “semiconductor IC device”) internally provided with a logic circuit and a memory circuit. More specifically, the present invention relates to a method of producing mask pattern data when designing circuit patterns for a semiconductor IC device, and an apparatus for carrying out the same method.
2. Description of the Prior Art
Demand for high-performance, low-power-consuming, compact semiconductor IC devices capable of advanced data processing operations for digital signal processing has increased in recent years. A recently proposed semiconductor IC device with built-in DRAM, one of the above-mentioned semiconductor IC devices, is provided with a random logic circuit and a dynamic random access memory circuit (referred to as “DRAM circuit”) formed on a semiconductor substrate
In the DRAM circuit, the substrate potential of an N-type MOS transistor forming part of a memory cell is a negative potential of, for example, about −1 V for stabilization through the enhancement of resistance to external noise. (Hereinafter, N-type MOS transistors charged at a negative substrate potential including the foregoing N-type MOS transistor will be generally designated as memory side N-type MOS transistors.) The substrate potential of N-type MOS transistors included in the random logic circuit is charged at a ground potential not to obstruct the enhancement of operating speed. (Hereinafter, such a transistor will be designated as logic side N-type MOS transistors.)
If a P-type semiconductor substrate (hereinafter referred to simply as “P-type substrate”) on which the DRAM circuit and the random logic circuit are formed is charged at a negative potential the same as the substrate potential. of the memory side N-type MOS transistors to stabilize the memory side N-type MOS transistors, the substrate potential of the logic side N-type MOS transistors must be electrically isolated from the P-type substrate.
In such a case, the logic side N-type MOS transistor is formed in a P-type well region (hereinafter referred to as “P-type well ”), and the P-type well and the P-type substrate are electrically isolated by an N-type well potential isolation region (hereinafter referred to as N-type isolation region”).
When designing such a semiconductor IC device with built-in DRAM by autoplacement and autorouting techniques, the layout of the N-type isolation regions must be determined by manually operating a mask pattern data producing apparatus (also called layout editor), namely, a circuit designing computer, after designing the random logic circuit and the DRAM circuit by autoplacement and autorouting techniques because information about the N-type isolation region does not include logical information describing the operations of the random logic circuit.
SUMMARY OF THE INVENTION
The present invention has been made to overcome the foregoing problems and has an object to provide a mask pattern data producing apparatus capable of automatically producing a mask pattern for the well potential isolation regions to reduce load on designing a circuit layout and of preventing artificial mistakes.
In addition, the present invention has another object to provide a mask pattern data producing apparatus capable of automatically producing data on wiring lines and contact holes necessary for supplying power to the well potential isolation regions to reduce labor and prevent artificial mistakes.
Further, the present invention has another object to provide a semiconductor IC device having a first IC and a second IC, and capable of applying a stable voltage to well potential isolation regions to avoid generating noise between the first and the second IC.
A mask pattern data producing apparatus according to a first aspect of the present invention comprises: a region specifying means for specifying a first IC forming region and a second IC forming region on a surface of a semiconductor substrate of a first type of conduction, the semiconductor substrate of the first type of conduction having the first IC forming region in which MOS transistors of a second type of conduction are formed in first well regions of a first type of conduction to be charged at a first substrate potential and the second IC forming region in which MOS transistors of the second type of conduction are formed in second well regions of the first type of conduction to be charged at a second substrate potential different from the first substrate potential;
a bottom well mask pattern producing means for producing a mask pattern for forming a bottom well of the second type of conduction under the first well regions in the entire first IC forming region of the semiconductor substrate; and
a well wall mask pattern producing means for producing a mask pattern for forming a well wall of the second type of conduction surrounding a first IC formed in the first IC forming region and extending from the surface of the semiconductor substrate to the bottom well on the basis of information about the first IC forming region specified by the region specifying means and information about the bottom well corresponding to the mask pattern produced by the bottom well mask pattern producing means.
A mask pattern data producing apparatus according to a second aspect of the present invention comprises: a region specifying means for specifying a first IC forming region in which a first IC is formed and a second IC forming region in which a second IC is formed, a semiconductor substrate of a first type of conduction having the first IC forming region and the second IC forming region, on a surface of the semiconductor substrate of the first type of conduction wherein the first IC comprises a plurality of cells designed in unit of logical level, at least some of the cells are formed of MOS transistors of a second type of conduction formed in first well regions of the first type of conduction to be charged at a first substrate potential, and at least part of the second IC is formed of MOS transistors of the second type of conduction formed in second well regions of the first type of conduction to be charged at a second substrate potential different from the first substrate potential;
a cell layout specifying means for specifying a layout of the plurality of cells in the first IC forming region on the basis of logical information describing the operations of the first IC;
a wiring route specifying means for specifying wiring routes in the first IC forming region on the basis of logical information describing the operations of the first IC and cell information about the plurality of cells;
a bottom well mask pattern producing means for producing a mask pattern for forming a bottom well of the second type of conduction under the first well regions in the entire first IC forming region of the semiconductor substrate; and
a well wall mask pattern producing means for producing a mask pattern for forming a well wall of the second type of conduction surrounding the first IC formed in the first IC forming region and extending from the surface of the semiconductor substrate to the bottom well through calculation using information about the first IC forming region specified by the region specifying means and information about the bottom well corresponding to the mask pattern produced by the bottom well mask pattern producing means.
A mask pattern data producing method according to a third aspect of the present invention comprises the steps of: allowing a region specifying means to specify a first IC forming region and a second IC forming region on a surface of a semiconductor substrate of a first type of conduction, the semiconductor substrate of the first type of conduction having the first IC forming region in which MOS transistors of a second type of conduction are formed in first well regions of a first type of conduction to be charged at a first substrate potential and the second IC forming region in which MOS transistors of the
Kanehira Yusuke
Naritomi Nobuhide
Satoh Takao
Jones Hugh
McDermott & Will & Emery
Mitsubishi Electric System LSI Design Corporation
Teska Kevin J.
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