Mask layout and method for forming vertical channel...

Details Mask layout and method for forming vertical channel... Mask layout and method for forming vertical channel...

2011-08-09

2011-08-09

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S197000, C438S296000, C257SE21051, C257SE21058, C257SE21135, C257SE21229, C257SE21231, C257SE21546, C257SE21551, C257SE21629, C257SE21640

Reexamination Certificate

active

07994061

ABSTRACT:
A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction.

REFERENCES:
patent: 7368352 (2008-05-01), Kim et al.
patent: 7670909 (2010-03-01), Cho
patent: 2007/0284623 (2007-12-01), Kim et al.
patent: 2009/0004797 (2009-01-01), Lee
patent: 2009/0114981 (2009-05-01), Sung et al.
patent: 2009/0163017 (2009-06-01), Cho
patent: 1020060041415 (2006-05-01), None
patent: 1020070009140 (2007-01-01), None
patent: 1020070047069 (2007-05-01), None
Korean Notice of Allowance for 10-2007-0136514, citing the above reference(s).

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