Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-27
2007-02-27
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10976001
ABSTRACT:
A photomask evaluating method comprises calculating a killer defect rate function with respect to a simulative defect pattern including a pattern of photomask and a plurality of defects, the killer defect rate function representing a killer defect rate of the simulative defect pattern with respect to a desired density of the pattern and a desired size of the plurality of defects, calculating the number of killer defects in an inspection region of the photomask based on an area of the photomask inspection region, a pattern density in the inspection region, the killer defect rate function and a defect size distribution representing the number of defects per unit area to a defect size range acquired from a photomask manufacturing step, and evaluating the photomask based on the calculated number of the killer defects.
REFERENCES:
patent: 6324481 (2001-11-01), Atchison et al.
patent: 6711733 (2004-03-01), Noda
patent: 2004/0115541 (2004-06-01), Yamaguchi et al.
patent: 2002-100548 (2002-04-01), None
patent: 2003-066590 (2003-03-01), None
Do Thuan
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
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