Mask data processor

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000

Reexamination Certificate

active

07020866

ABSTRACT:
Provided is a mask data processor capable of expanding a design data throughout the entire area of a mask. A storage device (MR) inputs a design data of sub-chips (D1) and mask data creation specification data (D2) to a pattern-density data generation device (10). Then, a data execution part (11) performs an arithmetic execution to the design data of sub-chips (D1) based on the mask data creation specification data (D2), followed by automatic mask data generation processing, layer arithmetic execution processing, and dummy pattern generation processing. When calculating a pattern graphic area, a graphic area calculation part (12) eliminates any overlap between graphics in order to avoid duplicate calculation. Based on the pattern graphic area, a pattern-density data calculation part (13) calculates the area ratios of graphic elements, i.e., pattern elements, contained in a unit region.

REFERENCES:
patent: 5436097 (1995-07-01), Norishima et al.
patent: 5923563 (1999-07-01), Lavin et al.
patent: 6093631 (2000-07-01), Jaso et al.
patent: 6711732 (2004-03-01), Dai et al.
patent: 2002/0078428 (2002-06-01), Lin
patent: 10-247206 (1998-09-01), None

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